|Optimizing LPDDR4 Performance and Power with Multi-Channel Architectures|
LPDDR4 offers huge bandwidth in a physically small PCB area and volume; up to 25.6 GByte/s of bandwidth at a 3,200 Mbps data rate from a single 15mmx15mm LPDDR4 package when two dies are packaged together. LPDDR4 builds on the success of LPDDR2 and LPDDR3 by adding new features and introducing a major architectural change. This white paper discusses why designers are selecting LPDDR4, how to handle 2-die and 4-die packages with multi-channel connections, the advantages of sharing channels through system-on-chip (SoC) partitioning, and how to optimize channels for the lowest power consumption.
Marc Greenberg, Director of Product Marketing for DDR IP, Synopsys
|Using an Embedded Vision Processor to Build an Efficient Object Recognition System|
The advent of high-performance mobile computing platforms is driving rapid progress in computer vision capabilities. Machine vision is becoming embedded in highly integrated SoCs and expanding into emerging high-volume consumer applications such as home surveillance, games, and automotive safety. A major challenge in enabling mass adoption of embedded vision applications is providing the processing capability at a power and cost point low enough for mobile consumer applications, while maintaining sufficient flexibility to cater to rapidly evolving markets. Read this whitepaper to understand the challenges of efficiently implementing an embedded vision system, explore an object detection application example and learn about the DesignWare Embedded Vision Processor Family.
James Campbell, CAE, Synopsys; Valeriy Kazantsev, CAE, Synopsys
|Rapid Architectural Exploration in Designing Application-Specific Processors|
Today’s SoCs demand increasing performance with high energy efficiency, but yet require flexibility to address late specification changes, post-silicon modifications and product derivatives. ASIPs close the gap between highly optimized fixed-hardware data path implementations and standard processor IP, and efficient architectural exploration is at the heart of any ASIP design process. Designers need to rapidly explore the impact of different architectural choices on power consumption and performance, ideally using real-world application C-code as part of the design flow. This white paper explains the architectural tradeoffs that are available to an ASIP designer, how to trade off performance vs. area, and why an ASIP design can still maintain full C-programmability while being optimized for a certain application domain. We will illustrate the architectural exploration approach using a simple yet representative example.
Bo Wu, Technical Marketing Manager, Synopsys; Markus Willems, Product Marketing Manager, Synopsys
|Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY-IP|
This white paper discusses how a MIPI M-PHY using High-Speed Gear3 operation can provide power-efficient high-speed links for a variety of mobile chip-to-chip communication standards and protocols, such as JEDEC Universal Flash Storage (UFS), USB 3.0 SuperSpeed Inter-chip (SSIC), and PCI-SIG M-PCIe®, each of which are optimized for its particular purpose. The paper then explains how designers can solve signal integrity challenges in implementation, including channel loss, interconnect, and electromagnetic interference (EMI) issues.
Sérgio Silva, Project Director, MIPI M-PHY IP, Synopsys, Inc. ; Hezi Saar, Product Marketing Manager, MIPI IP, Synopsys, Inc.
|SuperSpeed Your SoCs with USB 3.0 IP|
This whitepaper provides a comparison between the USB 3.0 and USB 2.0 standards, highlighting the new capabilities and advancements that have been made with this next-generation SuperSpeed USB standard including: performance, cables and connectors, power efficiency, USB model differences, hardware and software functionality, new protocol layers and streaming.
Dr. Robert Lefferts, R&D Director, Synopsys, Inc.; Subramaniam Aravindhan, R&D Manager, Synopsys, Inc.
|Delivering High Quality Analog Video Signals with Optimized Video DACs|
In most modern consumer equipment, multimedia content is processed in the digital domain. However, analog video transmission requires the digital video content conversion to the analog domain. To accomplish this, a video digital-to-analog (DAC) must be used. This paper outlines the most common analog video signal standard-specifications that multimedia SoCs must support. It describes the key characteristics and features of a DAC solution optimized for video applications. The paper addresses system-level techniques that together with an optimized video DAC will enable SoC designers to deliver power-efficient and feature-rich multimedia devices.
Antonio Leal, Analog Design Manager, Synopsys
|Solving the Integration Challenges for USB-Enabled Designs|
With power consumption and small form factors key issues, SoC designers must consider new requirements imposed by smaller technology nodes, especially for the USB PHY. This paper provides insights into dealing with these issues and profiles the USB IP offerings available from Synopsys.
Gervais Fong, Product Marketing Manager, Synopsys, Inc.; Eric Huang, Product Marketing Manager, Synopsys, Inc.
|Designing Application-Specific Processors for Wireless Baseband SoCs|
Traditional architectures for wireless baseband applications are no longer adequate for next-generation modem standards. Supporting multiple, evolving standards in a single modem is only possible by using SDR techniques, which place increasing demands on performance and power consumption on the SoC. ASIP architectures enable full customization of a processor, which allows design teams to better optimize their design’s wireless baseband SoCs. This white paper describes how tool-based ASIP design methodologies automate the generation of the software tool chain, including an optimized software compiler, and the generation of RTL for ASIC and FPGA implementation, which enables rapid architecture exploration and trade-off analysis between performance, power and area.
Bo Wu, Technical Marketing Manager, Synopsys, Inc.
|High Performance Connectivity IP: Avoiding Pitfalls When Selecting an IP Vendor|
The demand for connectivity IP for high-speed serial busses such as USB 2.0, PCI Express®, SATA, DDR2 and HDMI is increasing as standard interfaces in applications such as single chip recordable DVD CODECs and MP3 players. In order to stretch battery life of these chips, the semiconductor technologies require ultra-low power derivatives of high-performance logic manufacturing processes, enabling production of very low-power chips for these mobile platforms and small-form factor devices.
Navraj S. Nandra, Director of Product Marketing, Synopsys, Inc
|Low Power USB 2.0 PHY IP for High-Volume Consumer Applications|
The USB protocol has become a pervasive standard in the world of computing and consumer electronics. While few design teams would today contemplate designing their own USB IP this semiconductor IP is far from commodity silicon. Synopsys introduces a second USB 2.0 PHY IP product line (DesignWare® USB 2.0 nanoPHY), which has been further optimized for low power, area, manufacturing cost and system performance targeted at mobile and high volume consumer applications. This offers designers a choice of highly differentiated USB PHY cores for 0.13-micron processes and below.
Gervais Fong, Product Marketing Manager, Synopsys, Inc.
|A Method to Quickly Assess the Analog Front-End Performance in Communication SoCs|
This white paper outlines a simplified method to determine if the electrical characteristics of any given AFE are adequate for the targeted application such as broadband signal transceivers in the context of wireless or wireline connectivity, cellular communications and digital TV and radio broadcast. Additionally, it illustrates a tool to explore tradeoffs between relative performance and operating modes of different components to find the optimal performance, power, area and cost for SoCs.
Manuel Mota, Technical Marketing Manager, Synopsys, Inc.
|Scaling ADC Architectures for Mobile & Multimedia SoCs at 28-nm & Beyond|
This white paper compares the attributes of common ADC architectures, including the Successive Approximation Register (SAR)-based architecture, for use in medium- and high-speed 28-nm ADCs. It describes advantages of the SAR-based architecture that reduce power consumption and area usage for mobile and multimedia SoCs. Finally, it presents the DesignWare SAR-based ADC family for 28-nm and explains how it benefits from advanced process nodes through adherence to the area and power scaling paradigms of digital circuitry.
Carlos Azeredo-Leme, Analog Design, Senior Staff, Synopsys, Inc.; Pedro Figueiredo, Analog Design, Staff, Synopsys, Inc.; Manuel Mota, Technical Marketing Manager, Synopsys, Inc.
|Addressing Power and Speed Requirements of Mobile Devices with Data Converter IP|
To optimally address all the requirements for each application, there is a new generation of advanced data converter IP that includes Nyquist rate high-performance, high-speed ADC products, based on a highly optimized pipeline architecture. This paper describes the main power versus resolution trade-offs existing in the design of pipeline ADCs. It also discusses how digital gain calibration - one of the key techniques employed - eases those trade-offs, thus achieving significant improvements in power and area.
Pedro Figueiredo, Staff Engineer, Data Conversion, Synopsys, Inc.
|High Definition Video AFE: Far Beyond the ADC|
Based on the importance of the video AFE as an essential part of nearly any consumer video product or personal computing display and on the need that these products deliver the highest-quality images, this paper explains that, although it is possible to implement a video AFE from a stand-alone ADC and a collection of separate analog components, the complex interactions between them make developing an optimized system a difficult task which can add significant delay and risk to a design cycle. These risks can be reduced using an optimized video AFE core from a third party IP provider ensuring your design delivers the best possible video quality and power efficiency in all of the operating modes.
João Risques, Product Marketing Manager, Synopsys, Inc.
|CPU, GPU and DSP Core Optimization for High Performance and Low Power|
Each new process technology provides opportunities to optimize CPU, GPU and DSP processor core implementations to achieve better performance, power and area (PPA) results. This paper provides guidelines for establishing core design targets, selecting a design kit of standard cells and embedded memories and using implementation best practices to achieve PPA targets most efficiently.
Ken Brock, Product Marketing Manager, Synopsys, Inc.
|ARC HS38: Single- and Multicore CPUs for High-Speed Linux Processing on an Embedded Budget|
This white paper describes the Synopsys DesignWare® ARC® HS38 multicore processor for embedded Linux applications. The ARC HS38 processor is the latest addition to the ARC HS Family and adds several features including MMU, cache coherent symmetric multiprocessing and L2 cache. This whitepaper describes the key HS38 features for delivering high speed of operation with exceptional code density and power efficiency. Other topics covered include dual- and quad-core configurations, configurability options and instruction set architecture (ISA) extensibility that is unique to the ARCv2 architecture. This report was prepared by the Linley Group based on their analysis for the HS38 Processor.
Tom R. Halfhill, Senior Analyst, The Linley Group
|Building an Efficient, Tightly Coupled Embedded System Using an Extensible Processor|
The increasing demand for better filtering and processing capabilities of the processor within embedded systems results in a trend to shift from 8-bit microcontroller tightly coupled embedded systems towards 32-bit processor bus-based embedded systems, which has caused the power, performance and area (PPA) ratio of these systems to also shift in favor of performance at the cost of power and area. Closely coupled memories, together with ARC Processor EXtension (APEX) technology, provide a means to tightly couple memories and peripherals to an ARC processor core and make the area- and latency-expensive bus infrastructure redundant, reducing both the power consumption and area costs of the embedded system without sacrificing performance.
Jeroen Geuzebroek, Sr. R&D Engineer, Synopsys; Ad Vaassen, Sr. System Engineer, Synopsys
|Leveraging Processor Extensibility to Build an Ultra Low-Power Embedded Subsystem|
The ever increasing demand for smaller electronic devices, with more functionality, longer battery life, and shorter time to market has accelerated use of embedded processors and subsystems to offload the host processor from commonly executed tasks. Processor extensions provide a means to extend a general-purpose processor with custom hardware accelerators to optimize the execution of dedicated applications for reduced energy consumption and area, and/or increased performance. This white paper describes how processor extensions can optimize power and performance of a processor when targeting sensor applications, demonstrated using Synopsys’ DesignWare® ARC® Processors and ARC Processor Extensions (APEX) technology.
Jeroen Geuzebroek, Senior R&D Engineer, Synopsys
|The Linley Group: Synopsys ARC HS Processors: High-Speed Licensable CPU Cores for Embedded Applications|
This white paper describes the Synopsys DesignWare® ARC® HS (High Speed) processor family. ARC HS34 and HS36 are the first members of the company’s newest family of licensable CPU cores for embedded applications that need 32-bit RISC performance in a small silicon footprint with minimal power consumption. The Linley Group prepared this report after evaluating ARC HS performance data and technical features.
Tom R. Halfhill, Senior Analyst, The Linley Group; J. Scott Gardner, Senior Analyst, The Linley Group
|The Linley Group: DesignWare ARC EM Family: Efficient CPU Cores for Embedded Applications|
This paper describes Synopsys’ DesignWare® ARC® EM Processor Family, the company’s newest licensable CPU cores for embedded applications that benefit from 32-bit RISC performance with a tiny silicon footprint and minimal power consumption. According to vendor testing with EEMBC, SPEC, and other benchmarks, the newest ARC EM CPUs have excellent code density while delivering high performance using less power in a small silicon-area footprint. The Linley Group prepared this report after evaluating performance data and technical features for the recently upgraded EM4 and EM6 CPU cores.
J. Scott Gardner, Senior Analyst, The Linley Group; Tom R. Halfhill, Senior Analyst, The Linley Group
|Reduce Power, Area and Routing Congestion - Analysis of a High-Performance On-Chip-Bus Interconnect|
This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare® Interconnect Fabric for the ARM® AMBA® 3 AXI™ while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare® Interconnect Fabric used to meet the stringent timing requirements.
Fred Roberts, Corporate Applications Engineer, Synopsys, Inc.
|Save Up to 50% Dynamic Power on a GHz+ MIPS Core Implementation|
Dynamic power saving is a major challenge today for both mobile and wired applications with latest tools and technology processes/nodes. There are various options and factors to be considered for synthesizable or soft Intellectual Property (IP) designs. The same IP may be used in a wide variety of applications with different requirements across various sub-micron technologies. Also with advanced technologies based tools and flows, it adds another dimension of problems to be considered.The performance/area to power trade-offs varies from technology to technology. Also depends on customer implementation requirements. This paper evaluates various options from available sub-micron technologies, specifically 28nm and Synopsys tools and flow perspective.
Imagination Technologies and Synopsys