Galaxy Design Seminars
Accelerating IC Design from RTL to Silicon
These seminars provide a forum for members of the electronic design community to learn about Synopsys' latest technologies and methodologies. These FREE technical seminars will be focused on the latest developments within Synopsys' Galaxy™ Design Platform for IC implementation from RTL to silicon.
Who Should Attend
IC design engineers and managers who want to learn about new techniques to improve productivity and predictability.
What You Will Learn
You will learn about new capabilities available with the most recent Galaxy Design Platform tool releases and how to use them effectively to increase design productivity and achieve performance, power, and area and manufacturability goals. Seminar topics include RTL synthesis, design-for-test (DFT), physical design and verification, and signoff.
Galaxy Seminar Schedule
|May 14, 2014 ||Hsinchu, Taiwan ||Completed|
|May 21, 2014 ||Marlborough, MA ||Completed|
|July 10, 2014 ||Seoul, Korea ||Completed|
|August 18, 2014 ||Penang, Malaysia (See Agenda)||Completed|
|August 27, 2014||Boulder, Colorado||Completed|
|November 26, 2014||Cambridge UK||Registration Open|
|December 2, 2014||Bristol, UK||Registration Open|
|December 4, 2014||Eindhoven, Netherlands||Registration Open|
|December 9, 2014||Dublin, Ireland||Registration Open|
Seminar Agenda (may vary in some locations)
|Learn about the latest advancements and methodologies available in the Galaxy Implementation Platform, and how advanced designs targeting established and emerging process nodes can be implemented. New 2013.12 features, such as achieving better area, power and reduced congestion during synthesis, new route-based optimizations and improvements in concurrent clock and data optimization for physical implementation, achieving 2-3X faster signoff closure with simultaneous multi-corner extraction (SMC) and path-based timing analysis (PBA) will be introduced. In addition, hear how new ECO assistance in formal equivalence can be performed 2X faster and how making ECO changes during signoff, such as downsizing and buffer removal, reduces congestion and improves critical timing. Power optimization improvements for better QoR and a new Golden UPF methodology addressing ease-of-use will also be covered.|
|RTL Synthesis & Test|
This session covers the latest advancements and methodologies in RTL synthesis, equivalency checking and test. Innovative optimizations to achieve smaller area and lower leakage along with usability improvements, such as cross-probing and RTL analysis for efficient debugging will be presented. New 2013.12 release enhancements that improve timing, reduce congestion, and boost productivity for designs at established and emerging nodes will be discussed. Test cost reduction, enhancements to DFTMAX, logical equivalency checking and ECO implementation assistance with Formality will also be presented. Highlights include:
- 10% reduction in area and leakage delivers lower cost and power
- RTL analysis and cross-probing for efficient debugging
- Early congestion analysis enables faster routing
- 2X speed-up of functional ECO implementation with Formality Ultra
- 3X higher compression with DFTMAX Ultra
Learn about the technology advances in PrimeTime and StarRC that deliver the highest accuracy and fastest turnaround time in timing closure and signoff for advanced designs at emerging and established nodes. Highlights include:
- 2X faster runtime for extraction and timing analysis
- 2X faster ECO TAT with incremental extraction
- Automated IC Compiler-PrimeTime correlation flow/methodology
- Power (low voltage)
- Advanced CCS waveform propagation (w/SiS), SMVA, dynamic power ECO
- 2X faster static power analysis and early rail integrity analysis
- Area (reduced overdesign)
- ECO buffer sizing/removal for opening up space
- Tighter GBA-PBA correlation with lightweight statistical POCV analysis (w/SiS and IC Compiler)
|Physical Design & Verification|
|Learn about the new physical design capabilities in IC Compiler and the latest In-Design and signoff physical verification features in IC Validator. This session showcases the latest innovations in both tools that address advanced design at established and emerging nodes. High-performance designs will benefit from the new route-based optimizations and improvements in concurrent clock and data optimization. Enhanced multi-bit register support and low-power placement, along with golden UPF continue the focus on low-power design. IC Compiler capabilities that accelerate design closure, including data flow analysis, PrimeTime signoff correlation consistency checker and enabler, along with 10X faster incremental fill and ADR using In-Design will also be covered.|
IC Compiler and IC Validator are fully double-patterning (DPT) compliant and production-proven on FinFET-based designs and continue to provide enhancements for emerging-node designs. With its latest release, IC Compiler offers parametric OCV support and extended electromigration constraint coverage, while In-Design's new unified fill command automates dummy fill insertion that are pre-colored for double-pattering rules.
For signoff physical verification, IC Validator's performance improvements that provide options for memory footprint reduction and runtime speed-up will be covered. IC Validator also presents a much faster short extraction command, and new automated device extraction to simplify runset coding for LVS.