Galaxy Design Platform 

Accelerating Innovations in Advanced IC Design, Including 16nm  

The Galaxy™ Design Platform is a comprehensive solution for cell-based and custom IC implementation. Galaxy accepts design intent in industry standard formats and generates a production ready IC design in GDSII format. Galaxy RTL and Physical implementation products concurrently balance design constraints by performing intelligent tradeoffs between speed, area, power, test and yield. Galaxy Signoff engines accurately model complex physical interactions to ensure signal and power integrity. Coherent algorithms for parasitic extraction and timing produce correlated results.

The Galaxy™ Design Platform provides a comprehensive suite of tools that are being deployed worldwide targeting established process node designs as well as emerging process node FinFET designs at 20nm and below.

 

DC Explorer
Early RTL Exploration Accelerates Synthesis and P&R
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DC Ultra
Best-in-class timing, area and power QoR correlated with physical results
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Design Compiler Graphical
Extends topographical technology to predict & alleviate routing congestion
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Power Compiler
Provides complete solution for power synthesis & optimization
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DFTMAX
Adaptive scan compression for cost-effective DSM testing
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TetraMAX ATPG
Automatic test pattern generation & diagnostics for high-quality tests
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DesignWare IP
Reduce Risk and Speed Time-to-Market with High Quality IP


Formality
Equivalence checking for designs synthesized with DC Ultra
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IC Compiler II
Netlist to GDSII place and route system enabling 10X faster throughput



IC Compiler
Comprehensive place and route for established and emerging process nodes



Talus
Netlist-to-GDSII implementation for designs at or above 28nm


Custom Designer LE
Custom Layout editor
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Custom Designer SE
Custom Schematic Editor
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Custom Designer SDL
Custom design schematic-driven layout
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Laker Custom Design
Custom IC design and layout solution


Laker Blitz
Chip-level layout editor for chip finishing operations


Laker Flat Panel Display
Flat panel display editor


Laker Test Chip Development
Automated test chip development platform


Helix
Device-level placement for custom IC design
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PCell Xtreme
Persistent PCells for OpenAccess
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Titan Accelerators
Options for augmenting mixed-signal design flows


PrimeTime
Golden timing sign-off solution and environment
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NanoTime
Transistor-level STA for custom design
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StarRC
Parasitic extraction
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StarRC Custom
Unified gold standard extraction including Rapid3D fast field solver
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PrimeRail
In-Design Rail Analysis for Place-and-Route Engineers
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SiliconSmart
Advanced cell characterization 
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Liberty NCX
Composite current source modeling and library delivery system
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IC Validator
In-design physical verification solution for 45nm and below
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Hercules
Technology-leading physical verification for 45nm and above


PrimeYield LCC
Accurate, production-proven lithography compliance checking

  • SDC
  • Synopsys Design Constraints more

 
Essentially all synthesized designs use SDC and numerous EDA companies have translators that can read and process SDC.

Key Benefits
  • Production proven down to 16nm
  • Optimal trade-offs between speed, area, power, test and yield.
  • Industry standard sign-off timing and extraction
  • Unmatched 3rd party support for technology libraries, services and IP.
  • Provides fastest path to the best results

Design Challenges
Physical effects of semiconductors are becoming more and more interrelated. Each design decision can create unintended consequences. In addition to the old problems generated by wire capacitance, engineers can no longer manually balance the myriad effects such as leakage current, inductive noise or IR drop. Manufacturing processes and environmental variation can render your functional chip useless or economically unviable. Market forces are creating demands of higher volumes at lower and lower price points. Investors are losing their appetite for risk and paying a premium for predictable success. Designers must walk a tightrope of price and performance to reach their time-to-market goals.

Exponential advances of Moore’s Law have facilitated creative solutions to the very problems they have created. Advances in computing power coupled to innovative algorithms enable the Galaxy Design Platform to perform two essential functions:
  1. Accurately model physical effects to guarantee timing
  2. Concurrently evaluate trade-offs between design goals

Accurate modeling of physical effects such as noise and power enable the advanced algorithms of the Galaxy platform to push the envelope of achievable performance and minimize the drain of pessimistic margins. This extra performance is like money in the bank. The concurrent optimization engines spend this savings to minimize power consumption, reduce area, lower test costs or increase yield. All of this increases productivity by saving time and iterations spent on fixing unintended consequences.

The Galaxy Platform lets designers do what they do best – design!



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