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Faster Timing Closure with the Lynx Design System
Using the Lynx Design System, you will learn how to leverage the advanced timing closure features available with Synopsys’ IC Compiler and PrimeTime.
Aditya Ramachandran, Lynx CAE, Synopsys
May 09, 2012 | | | Enabling 20nm Design: A Foundry and EDA Perspective
TSMC and Synopsys will jointly present some of the key design and manufacturing challenges at 20nm process technology. They will highlight the need for early collaboration between EDA, customers and the foundry to ensure a smooth path to tape-out and first-time silicon success.
Willy Chen, Department Manager, Design Methodology & Service Marketing Program R&D, TSMC; Dr. Tong Gao, Synopsys Fellow, Synopsys
May 01, 2012 | | | Faster PrimeTime Signoff - Tips, Tricks and New Technology
Learn how to achieve a 2X reduction in signoff TAT, and build the expertise to create high-performance signoff scripts.
Tzong-Maw Tsai, CAE Director, Synopsys; Amrita Sahoo, Senior Corporate Applications Engineer, Synopsys
Apr 25, 2012 | | | Efficient Clock Distribution: A Critical Factor in Design Performance
Synopsys and LSI jointly present on designing today’s high frequency, low power clocks. LSI will present their perspective on the challenges of clock distribution and Synopsys will focus on the solutions that enable designers to achieve the best QoR and lowest power at today’s advanced technology nodes.
JC Parker, Senior Director of Design Tools and Methodologies, LSI; Dennis Ding, R&D Director, Synopsys
Apr 04, 2012 | | | Streamlining Your ECO Flow For Fastest Setup, Hold and Timing DRC Closure
Learn what’s new with timing-aware DRC guidance for ECOs and which design flow and tool settings provide the fastest timing closure at 28 nm and below.
Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys; Vivek Ghante, Staff Corporate Applications Engineer, Implementation Group, Synopsys
Mar 14, 2012 | | | Managing Hierarchical, Low Power Design Challenges with the Lynx Design System
In this seminar, we will demonstrate silicon-proven methodologies to describe power intent with IEEE 1801 (UPF) using a hierarchical design flow to address power consumption and design size concurrently. We will walk you through some of the key steps in implementing and analyzing a hierarchical design using UPF for both bottom-up and top-down Synopsys Galaxy-based flows.
Chad Gamble, Synopsys
Jan 17, 2012 | | | Get the Most from Your HSPICE Simulation
Unleash the power of HSPICE simulations with useful tips and tricks to reduce simulation time without compromising HSPICE’s gold-standard accuracy.
Szekit Chan, HSPICE Staff Corporate Applications Engineer, Synopsys
Nov 30, 2011 | | | Understand and Avoid Electromigration (EM) & IR-drop Effects in Custom IP Blocks
Learn how process technology & changing design styles increase the impact of EM & IR-drop effects on the performance/reliability of AMS, memory & custom digital IP blocks at 28nm and below.
Bradley Geden, Solution Architect, Synopsys
Oct 26, 2011 | | | Faster Clock Analysis and Debug
Learn how to save time using Galaxy Constraint Analyzer and PrimeTime to ensure clean clock constraints and keep clocks free of timing violations during signoff.
Karen Linser, Staff Corporate Applications Engineer, Implementation Group, Synopsys; Robert Landy, Staff Corporate Applications Engineer, Implementation Group, Synopsys
Oct 25, 2011 | | | Extraction Features & PDKs for Accurate Analog Design
Learn how StarRC new custom design features including 3D symmetric net extraction, optimized PCELL solution, and qualified PDK support, enable accurate and productive analog/mixed-signal design.
Krishnakumar Sundaresan, Principal Engineer/Manager, CAE, Synopsys
Oct 20, 2011 | | | Use IC Compiler and Custom Designer to Shave Weeks Off Your SoC Development Cycle
Learn how the seamless integration between IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits at any stage of development.
Chris Shaw, Sr. Technical Marketing Manager, Synopsys;
Denis Goinard, CAE Manager, Synopsys
Oct 19, 2011 | | | Save Weeks Fixing ECOs with PrimeTime and IC Compiler
See how design teams are saving weeks during implementation and signoff. Learn how PrimeTime Next-Generation ECO guidance and IC Compiler automatically fix DRC, setup and hold violations to reduce it.
Troy Epperly, Staff Engineer, CAE, Implementation Group, Synopsys; Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys
Jul 20, 2011 | | | Optimize in Less Time: Rapid Design Exploration with Lynx Design System
Every SoC design requires a unique implementation strategy to navigate the tradeoffs between power, performance and area to achieve the best results for the specific use.
Aditya Ramachandran, CAE, Lynx Design System, Synopsys
Jul 19, 2011 | | | Fast Timing Constraint Cleanup with Galaxy Constraint Analyzer
Learn how Galaxy Constraint Analyzer helps to produce signoff-quality timing constraints quickly, for even the most complex designs. Hear how AMD uses Galaxy Constraint Analyzer for quality assurance.
Richard Bishop, Member of Technical Staff, AMD; Karen Linser,
Senor Corporate Applications Engineer, Implementation Group, Synopsys
May 18, 2011 | | | Advanced Regression and Analysis for Mixed-Signal Verification Using CustomExplorer Ultra
Learn how CustomExplorer Ultra enables high verification productivity for complex SoCs using advanced strategies that surpass traditional verification approaches.
Duncan McDonald, Product Marketing Manager, Synopsys; Dwayne Holst, Corporate Applications Engineer, Synopsys
May 11, 2011 | | | Accurate Jitter and Noise Analysis Using HSPICE Transient Noise Techniques
Learn about new time-domain noise analysis approaches available in HSPICE, and how transient noise analysis can verify critical timing and noise performance characteristics.
Scott Wedge, Sr. Staff Engineer, Synopsys
May 04, 2011 | | | StarRC High Performance Multicore and Hierarchical Extraction
Learn the details of the faster multicore architecture, and the techniques to achieve best correlation between hierarchical and full-chip flat extraction.
Krishnakumar Sundaresan, Principal Engineer/CAE Manager, StarRC, Synopsys; Beifang Qiu, Senior R&D Manager, StarRC, Synopsys
Apr 26, 2011 | | | Debug Timing Faster with PrimeTime Visualization Tools
Save time debugging complex timing paths during implementation and signoff using new visualization techniques in PrimeTime. See new clock and data analysis capabilities in action.
Robert Landy, Staff Corporate Applications Engineer, Implementation Group, Synopsys; Philip Cuney, Design Support Technical Leader, Design Support & Methodology Group, Home Entertainment & Displays, ST Microelectronics
Apr 20, 2011 | | | Noise Analysis and CCS Noise Model Generation for Custom Digital Designs
Learn how the advanced features in NanoTime enable designers to accurately and quickly identify timing issues early in the design cycle to avoid expensive silicon re-spins.
Chirag Patel, Staff Engineer, CAE, Synopsys; Peter O’Brien, Senior Staff R&D Engineer, Synopsys
Apr 13, 2011 | | | From Advanced OCV to UPF: Superior Results with the Lynx Design System
In this webinar you will learn how the built-in features of the Lynx Design System can help you achieve predictable design closure with superior results for low power chips.
Aditya Ramachandran, Lynx Design System, CAE, Synopsys; Neel Desai, Lynx Design System, Product Marketing Manager, Synopsys
Apr 12, 2011 | | | Reducing Design Margins Using PrimeTime Advanced OCV – TSMC and User Views
Learn how designers are using PrimeTime Advanced OCV to speed design closure by eliminating overly pessimistic violations, and hear about TSMC’s views and support model for these new technologies.
Willy Chen, Program Manager, Design Methodology Division, TSMC; Norb Heindl, Senior Staff Engineer CAE, Implementation Group, Synopsys
Feb 23, 2011 | | | Advances in Circuit Analysis with the Custom Designer Simulation and Analysis Environment
Learn how to efficiently use Custom Designer's SAE in conjunction with HSPICE and Custom WaveView to analyze a design across process and parameter variations.
Kristin Beggs, R&D Engineer, Synopsys
Oct 27, 2010 | | | Accelerate Analog Simulation with HSPICE Precision Parallel Technology
Learn how HSPICE Precision Parallel technology accelerates verification of analog/mixed-signal circuits up to 7X on 8 cores while maintaining gold-standard accuracy.
Hany Elhak, Product Marketing Manager, Synopsys; Fredrik Ivarsson, Corporate Applications Engineer, Synopsys
Oct 20, 2010 | | | 28nm Silicon and Design Enablement – A Foundry and EDA Vendor Perspective
In this final webinar of the 32/28nm design series, Synopsys and GLOBALFOUNDRIES share their perspectives on 28nm process technology and design enablement and 32/28nm design solutions respectively.
JC Lin, Vice President of Engineering, Synopsys and Walter Ng, Vice President, IP Ecosystem, GLOBALFOUNDRIES
Oct 13, 2010 | | | Take Control of Your Design With the Lynx Design System
Learn how the Lynx Design System, including a production flow, the ability to pre-validate libraries and technology data, and project tracking and reporting features, helps control your design schedule!
Aditya Ramachandran, CAE, Synopsys; Neel Desai, Product Marketing Manager, Synopsys
Aug 25, 2010 | | | Multi-Gigabit Signal Integrity Analysis with HSPICE
Learn about HSPICE capabilities for modeling high-frequency channel components, and high-performance simulation and analysis features for characterizing multi-gigabit links.
Scott Wedge, Ph.D, Sr. Staff Engineer, Synopsys
Aug 18, 2010 | | | Manufacturing-Aware Routing at 32/28nm
Considering yield as one of the objectives during design has become a necessity at the 32/28nm node. In this webinar, you will learn techniques for addressing manufacturing during routing with IC Compiler’s Zroute technology which considers manufacturability as a routing objective.
Dr. Tong Gao, Synopsys Fellow, Synopsys; Yukti Rao, Product Marketing Manager, Synopsys
Aug 11, 2010 | | | Accurate Power Analysis of Low Power Techniques Using PrimeTime PX
This technical webinar will explain how PrimeTime PX can be used to analyze the effectiveness of low power design techniques such as clock gating, use of multi-voltage rails and power gating. Attendees will learn how to further optimize their designs for power by analyzing which low-power techniques work best under differing conditions. You will also learn how to use PrimeTime PX to understand which modes of operation consume the most power.
David Le, Senior Manager, CAE, Implementation Group, Synopsys; Maria Tovey, Staff Engineer, CAE, Implementation Group, Synopsys
Aug 03, 2010 | | | Realizing Today’s 32nm and Beyond Large Capacity Designs
Synopsys Design Planning R&D will highlight the latest hierarchical design exploration and planning technology available in IC Compiler for handling today’s large 32/28nm designs.
Thomas Andersen, Director of R&D, IC Compiler, Synopsys; Mark Bollar, Director of Product Marketing, IC Compiler, Synopsys
Jul 28, 2010 | | | Find Electrical Violations Before Tapeout with CustomSim Circuit Check
Learn how customers are using CustomSim Circuit Check to analyze designs with hundreds of millions of transistors to catch electrical violations before tapeout.
Bradley Geden, Product Marketing Manager, Synopsys
Jul 21, 2010 | | | Faster ECO Fixing Flows with PrimeTime and IC Compiler
This technical webinar will explain how IC Compiler and PrimeTime can be used to close timing during signoff. It will focus on the use of Distributed Multi-Scenario Analysis for automatic set-up and hold fixing, and will explain new PrimeTime 2010.06 DRC fixing capabilities. Attendees will learn how to minimize fixing run times, which approaches are best for closing setup and hold violations, and how to deploy SI fixing most effectively.
Uyen Tran, Director, CAE, Implementation Group, Synopsys; Jennifer Pyon, Senior Staff Engineer, CAE, Implementation Group, Synopsys
Jul 20, 2010 | | | Eliminating Late-Stage DRC Surprises with In-Design Physical Verification
Third in the In-Design technology series featuring several high productivity in-design physical verification flows with IC Validator, including Automatic DRC Repair and Pre-Routing Verification – all from within IC Compiler.
Kerstin McKay, CAE Director, Physical Verification, Synopsys
May 05, 2010 | | | Shaping the Perfect Audio Codec: How Your SoC Can Benefit from the Right Audio Functions’ Line-Ups
In this webinar, you will get an overview of a wide range of audio functions that can be optimized for low power consumption and small silicon area such as volume control, high isolation inputs, crosstalk, headset drivers, Class-G, pop-noise suppression and clock management. You will also learn how to select the right analog audio block lineups for different types of applications, and you will understand how Synopsys’ high-quality DesignWare Audio IP solutions can deliver performance levels at par with those from discrete components
João Risques, Product Marketing Manager , Synopsys
Apr 13, 2010 | | | Verify Digitally-Assisted Analog Circuits with CustomSim Fast Transient Analysis
Learn how the CustomSim high-capacity, fast transient analysis solution can help you increase design confidence and reduce project development time.
Bradley Geden, Product Marketing Manager, Synopsys; Tom Hsieh, AMS CAE, Synopsys
Mar 25, 2010 | | | Custom Designer: Advances in Custom Layout Automation with SmartDRD
SmartDRD technology visualizes, prevents and automatically fixes DRC violations to help designers quickly achieve DRC clean designs with significantly reduced effort.
Marc Swinnen, Sr. Product Marketing Manager, Synopsys; Christopher Shaw, Technical Marketing Manager, Synopsys
Mar 23, 2010 | | | Reducing Design Margins Using PrimeTime Advanced OCV
How Advanced On-Chip-Variation works in comparison to flat-derate OCV and SSTA-based signoff technologies. Techniques for deploying PrimeTime to reduce pessimistic endpoints and slack pessimism.
Uyen Tran, Director CAE, Synopsys; Norb Heindl, Senior Staff Engineer, CAE, Synopsys
Feb 17, 2010 | | | Addressing Signal Integrity Noise in Low Power Design
A discussion on the impact of low power design and the resulting requirements that drive the technologies in today’s static timing analysis tools. Learn about PrimeTime SI techniques that will enable you to deploy the SI noise-aware flow that best fits your needs for fast, accurate signoff.
Tzong-Maw Tsai, Director, Corporate Applications Engineer, Synopsys;
Troy Epperly, Corporate Applications Engineer, Synopsys
Jan 20, 2010 | | | HSPICE/Custom Designer for Analog & RF Circuit Design
Analog/RF design solution helps meet design challenges
Christopher Labrecque, HSPICE Marketing Manager, Synopsys; Fredrik Ivarsson, Custom Design Corporate Applications Engineer, Synopsys
Nov 05, 2009 | | | Front-to-Back AMS Flow using Custom Designer
Follow the front-to-back development of an AMS block using Synopsys' Galaxy Custom Designer implementation solution.
Joe Mastroianni, VP of R&D, Les Spruiell, Product Marketing Manager, Synopsys; Chris Shaw, Technical Marketing Manager, Synopsys
Nov 03, 2009 | | | IC Compiler Ecosystem
There is a thriving ecosystem around IC Compiler and the Galaxy Implementation Platform products engineered to work together to speed design closure. Hear from designers who share how they have relied on the IC Compiler ecosystem to achieve faster time to results and improved productivity.
JC Lin, Synopsys
Oct 31, 2009 | | | Faster Power/Ground Grid Closure with In-Design Rail Analysis
Join our experts to learn how you can use In-Design Rail Analysis to analyze and debug voltage drop, power up and electromigration (EM) effects as early as placement, helping you accelerate the path to final design closure.
Tom Chau, Group CAE Director, Synopsys; Dr. Henry Sheng, R&D Group Director, Synopsys
Jun 25, 2009 | | | Faster Design Closure with Congestion Minimization
This webinar will show you how predictable routing congestion from synthesis to tapeout eliminates unnecessary iterations, speeding up your overall turnaround time.
Janet Olson, Synopsys
Jun 09, 2009 | | | Lynx Product Overview & Demo
This one-hour webinar includes a brief overview presentation on Lynx followed by a detailed product demonstration. For more information on the Lynx Design System, visit: www.synopsys.com/Lynx.
Neel Desai, Product Marketing Manager, Lynx Design System, Synopsys
Jun 03, 2009 | | | In-Design PV for Faster Time-to-Tapeout
Synopsys’ physical design and verification technologists will show you how in-design physical verification combines timing awareness and signoff accuracy to speed up your tapeout schedule.
Kerstin McKay, CAE Director, Physical Verification products, Synopsys
May 20, 2009 | | | Accelerating Time-to-SI Closure
View this webinar to learn how to use signoff-driven SI-closure to keep your schedule on track and your performance on target.
Dr. Henry Sheng, Synopsys; Dr. Jinan Lou, Synopsys
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