Galaxy Implementation Seminars 

Accelerating Gigascale Technology 
Check the Galaxy Seminar Schedule for a location near you.

Seminar Overview
This worldwide seminar series provides a forum for members of the electronic design community to learn about Synopsys’ latest technologies and methodologies. The FREE technical seminars are intended for IC design engineers and managers, and will be focused on the latest developments within Synopsys’ Galaxy™ Implementation Platform for IC implementation from RTL to silicon.

Who Should Attend:
IC design engineers and managers who want to learn new techniques to improve productivity and predictability.

What You Will Learn:
You will learn about new capabilities available with the most recent Galaxy ™ Implementation Platform tool releases and how to use them effectively to increase design implementation productivity and achieve performance, power, and area and manufacturability goals. A full day seminar includes RTL synthesis, design-for-test (DFT), physical design and verification, and signoff. Low Power is included in select locations only.

Primary Seminar Agenda (may vary by location) - check here for detailed seminar topic descriptions:

Time
Topic
9:15 a.m.Registration and welcome
9:30 a.m.Galaxy Implementation Overview
10:30 a.m.Break
10:45 a.m.RTL Synthesis and Test
12:15 p.m.Lunch (provided by Synopsys)
1:15 p.m.Physical Design and Verification
3:30 p.m.Signoff
4:45 p.m.Wrap-up and Gift Drawing

Galaxy Seminar Schedule:

Date
Location
Registration
May 1, 2013
Irvine, Synopsys
CLOSED
May 7, 2013
Hsinchu, Taiwan
CLOSED
May 10, 2013
Shanghai, China
CLOSED
May 13, 2013
Shenzhen, China
CLOSED
May 15, 2013
Beijing, China
CLOSED
June 11, 2013
Marlborough, MA
CLOSED
June 18, 2013
Columbia, MD
CLOSED
August 12, 2013
Penang, Malaysia

*Check here for Seminar Agenda in Penang

Seminar Topic Descriptions:

Topic and Duration
Abstract
Galaxy Overview (60 mins)
Hear about the latest technologies throughout Synopsys’ Galaxy™ Implementation Platform of products and how they help customers accelerate innovation. Highlights of the latest features in synthesis, physical design, In-Design physical verification, fast multi-scenario extraction, high-performance static analysis and efficient analog mixed signal co-design will be provided. This session will also provide insights on high-performance and low-power design technologies to achieve the best quality of results. Additionally, you’ll learn how collaborative efforts have resulted in a comprehensive advanced geometry solution for 20-nanometer and below designs, including FinFET transistors.
RTL Synthesis and Test (90 mins)
This session highlights the 2013.03 features of the Design Compiler® product family that can help you to improve circuit quality and reduce turnaround time. You will learn how DC Explorer enables early RTL exploration, floorplan and data flow analyses leading to a better starting point for synthesis. You will see how the advances in Design Compiler Graphical can help you to achieve better quality-of–results and a more predicable design implementation. The session will also highlight how DFTMAX™ provides more cost-effective testing of ARM processor-based designs and other multicore SoCs, and how you can perform complete verification of these designs with Formality®.
Signoff (70 mins)
This session highlights the new technologies in PrimeTime® and StarRC™ which address the demand for faster turnaround time in extraction and timing closure for ECO and sign-off design flows. We’ll introduce you to the latest advances in performance and capacity, and new parasitic modeling features to address challenges at 20 and 14 nm. Signoff enhancements include technology for scenario reduction, enhanced constraint analysis, ECO enhancements to add leakage recovery and further improve timing fix rates, and new margining methodology to improve runtime whilst maximizing accuracy; all to boost productivity and ensure accuracy in gigascale and gighertz design flows.
Physical Design and Verification (135 mins)
This session focuses on both the new physical design capabilities in IC Compiler™ and also the latest In-Design and signoff physical verification features in IC Validator. The presentation showcases IC Compiler technologies that accelerate design closure for today’s complex designs. It will highlight new capabilities enabling faster design closure such as Dataflow Analysis and Minimum Physical Impact ECO. High-performance designs will benefit from the technology advancements in placement and clock and data optimization while a low power focus will be addressed through multibit register support and improved timing/leakage optimization. In addition, IC Validator’s In-Design capabilities that accelerate design closure with a fully automatic incremental DRC checking and incremental metal fill insertion flow will also be covered.

Both tools provide latest finFET technologies with expanded double patterning support for a color-ready design and enhanced fill-to-target methodology for density management. The presentation will show how full-chip signoff with IC Validator has been accelerated with adaptive threading for better multi-CPU scalability and a new LVS-aware short finder.



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