|Verilog-to-Verilog Equivalence Checking Using ESP|
This Webinar gives a quick introduction to ESP-CV and how recent features are used to verify various Verilog-to-Verilog scenarios. Coverage analysis of the results is also discussed.
Philip Schmidt, R&D Manager, Synopsys; Dave Hedges, Corporate Applications Engineer, Synopsys
May 29, 2013
|Transaction Debug with Verdi3|
In this webinar, you'll learn how to maximize your productivity by using Verdi's Transaction Debugging technology to dump, visualize and trace transactions. You'll learn how the tool's vertical correlation allows you to take the debug to the signal level waveform while retaining all of the necessary debugging details.
Rich Chang, Product Marketing Manager for Debug, Synopsys
May 22, 2013
|Discovery-AMS for Mixed-Signal Verification - An ST-Ericsson Case Study|
ST-Ericsson shares details on how they leveraged new Discovery-AMS multi-core technology to improve their overall verification flow.
Francois Ravatin, AMS Verification Engineer, ST-Ericsson; Helene Thibieroz, Sr. Product Marketing Manager, Synopsys
May 21, 2013
|Verifying Advanced Low Power Designs: Find Design-Killing LP Bugs Early and Easily|
Learn how VCS with MVSIM Native Low Power provide the accuracy and comprehensive LP support needed at RTL, and enable LP bugs to be found and fixed early and easily in the design cycle.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Aditya Kher, Senior Corporate Application Engineer (CAE), Low Power Verification, Synopsys; Harsh Chilwal, Senior R&D Engineer, Synopsys
Apr 04, 2013
|Accelerate PCIe Integration Testing with Next-Generation Discovery VIP|
Learn an optimal strategy for integration testing using UVM in conjunction with next-generation features of PCIe VIP for more efficient test development, error injection and debug.
Neill Mullinger, Product Marketing Manager, Synopsys; Paul Graykowski, Corporate Application Engineer (CAE), Synopsys
Mar 20, 2013
|Functional Signoff: Measuring and Improving Verification Quality to Ensure Bug-Free Designs|
In this webinar you will learn how Certitude Functional Qualification can be added to traditional coverage techniques, to provide unique insight into the quality of RTL simulation and formal verification environments. Certitude uses a proprietary mutation-based process to insert “artificial bugs” or faults into the design and measure the ability of your existing verification environment to detect these faults. The results of this process provide an objective measure of overall verification quality – the ability of the environment to activate, propagate and detect potential bugs – and identify specific holes and weaknesses like incomplete test scenarios, missing checkers and assertions, or infrastructure problems that can allow RTL bugs to slip through the process undetected. Fixing these weaknesses makes your verification environment stronger and reduces the risk of signing off or taping out with functional bugs.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; George Bakewell, CAE Director, Verification Group, Synopsys
Jan 10, 2013
|Using Advanced Verification IP Capabilities to Accelerate Ethernet Verification|
This webinar will be based around a typical Ethernet switch design including a processor, switch fabric and Ethernet MACs. Learn how SystemVerilog, UVM and VIP are utilized to verify the Ethernet digital core and then integration of the core into the system. We also cover advanced VIP features, including test suite and debug, to accelerate productivity.
Neill Mullinger, Product Marketing Manager for Verification IP,
Synopsys; Jaspreet Singh Gambhir, R&D Manager for Verification IP, Synopsys
Dec 11, 2012
|Static Verification of Advanced Low Power Designs|
Learn about advanced low power techniques and the static checking capabilities designers need to verify the consistency and correctness of low power intent and implementation through the flow.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Vinay Srinivas, R&D Group Director, Low Power Verification, Synopsys; Prapanna Tiwari , CAE Manager, Low Power Verification, Synopsys
Oct 30, 2012
|Open Your Eye with HSPICE Fast and Accurate Eye Diagram Analysis|
Learn how HSPICE can help you quickly model high-frequency channel components, run fast transient with long cable S-parameter models, and accurately analyze eye measurement.
Ted Mido, Sr. Staff R&D Enigeer, Synopsys
Oct 17, 2012
|Eliminate the Digital Implementation Bottleneck with Fast and Accurate Library Characterization|
Learn how SiliconSmart can help you produce accurate model libraries that are tightly correlated with Synopsys' digital implementation tools and PrimeTime
Eduardo Flores, Staff Applications Consultant, Synopsys; Surbhi Agarwal, Product Marketing Manager, Synopsys
Oct 16, 2012
|Deploying UVM Effectively: How to Simplify Testbench Debug and Improve Turn-around-time with VCS|
Learn how to utilize VCS and DVE to most effectively deploy, debug and optimize UVM testbenches.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; Adiel Khan, Corporate Applications Engineer (CAE), Verification Group, Synopsys
Oct 02, 2012
|Verification of MIPI Protocols on a Mobile Platform SoC|
This webinar is based around a MIPI-based mobile platform that consists of an application processor, baseband IC and RF IC with interfaces to the peripheral devices like camera, and display. The Webinar shows how SystemVerilog, UVM and verification IP (VIP) are utilized to verify the SoC that implements that platform. It will specifically focus on how to validate the data flow for typical scenarios involving the camera (CSI) and display (DSI) interfaces.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Narasimhababu GVL, Senior R&D Manager for Verification IP, Synopsys
Aug 07, 2012
|High-Productivity Analog Verification and Debug with CustomSim and CustomExplorer Ultra|
See how Synopsys' advanced analog verification solution can dramatically increase your verification productivity with CustomExplorer Ultra, along with CustomSim and CustomSim-VCS.
Duncan McDonald, Product Marketing Manager, Synopsys
Jul 11, 2012
|Achieving Rapid Verification Convergence of ARM® AMBA® 4 ACE™ Designs using Discovery™ VIP|
Overview of challenges of verifying a coherent design. Shows how the features and architecture of Synopsys’ new Discovery VIP helps overcome these challenges to simplify verification of ACE design.
Abhijeet Khopkar, R&D Manager, Synopsys; Neill Mullinger, Group Marketing Manager, Synopsys
May 08, 2012
|Get the Most from Your HSPICE Simulation|
Unleash the power of HSPICE simulations with useful tips and tricks to reduce simulation time without compromising HSPICE’s gold-standard accuracy.
Szekit Chan, HSPICE Staff Corporate Applications Engineer, Synopsys
Nov 30, 2011
|Understand and Avoid Electromigration (EM) & IR-drop Effects in Custom IP Blocks|
Learn how process technology & changing design styles increase the impact of EM & IR-drop effects on the performance/reliability of AMS, memory & custom digital IP blocks at 28nm and below.
Bradley Geden, Solution Architect, Synopsys
Oct 26, 2011