The guest panel of industry experts discussed how they are addressing key verification challenges at 32 nanometers, achieving high-accuracy verification for complex BCD and FPGA applications, and using power management techniques for custom DSP designs.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys; Aaron Barker, Staff Engineer, Sun Microsystems; Eugene Chen, CAD Director, Alter; Sandeep Tare, Verification Methodology Engineer, Texas Instruments; Lyes Djama, Smart Power Design Flows Manager; Pierluigi Daglio, AMS Design & Verification Flows Manager, STMicroelectronics

Synopsys hosted a special VCS Verification Luncheon event at DAC in San Francisco, CA focused on the VCS functional verification solution. Verification R&D experts from leading companies discussed how they leverage VCS’s multicore performance, transaction-based verification, tight mixed-signal integration, comprehensive low power verification capabilities and proven methodologies to solve today’s toughest verification challenges.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys; YC Wong, Director of IC Engineering, Broadcom; Shrenik Mehta, Sr. Director of Frontend Tools and OpenSPARC, Sun Microsystems; Faisal Haque, Director of Engineering, Qualcomm; and Amit Chowdhry, Member of Technical Staff, AMD

Need for a Low Power Verification Methodology. Learn about ARM and Synopsys’ joint efforts to develop a Verification Methodology for Low Power Designs.
Alan Hunter, Verification Methodology Lead

DOWNLOAD PRESENTATION (PDF)

Low Power Verification User Experience See a presentation on the unique challenges of low power design verification and how they are being addressed by Reneses using Synopsys' tools.
Yoshio Inoue, Chief Engineer

DOWNLOAD PRESENTATION (PDF)

Engineering the APX2500: Verification Methodology for Low Power Watch a presentation on NVIDIA’s experience using the Verification Methodology for Low Power Design on the APX2500, the world’s lowest power, high definition video and graphics computer on a chip.
Soma Bhattacharjee, Director of Engineering

DOWNLOAD PRESENTATION (PDF)

"Are We There Yet?" Listen to a discussion on VMM Planner and how IBM used it on their BIST project to determine when they had run enough random tests.
Nancy Pratt, BIST Verification Lead

DOWNLOAD PRESENTATION (PDF)