Videos 

2012 HSPICE SIG Event: Tackling Design Integrity of Multi-Gbps Systems
2012 HSPICE SIG Event: Tackling Design Integrity of Multi-Gbps Systems

On January 31, 2012, Synopsys hosted an HSPICE SIG Event in Santa Clara, CA. At this event, industry leaders spoke about their experiences using HSPICE in some of their most challenging designs.
Tony Todesco, SMTS Design Engineer, AMD; Johann Nittman, Signal Integrity Engineer, Cavium Networks; Liping Li, Sr. Member of the Technical Staff, Altera; Randy Wolff, Manager, Signal Integrity R&D Group, Micron; Scott Wedge, Sr. Staff Engineer, Synopsys



DAC 2011: SPICE Up Your Chip: Achieving Fast, Accurate AMS Verification

On June 7, 2011, Synopsys hosted an dinner event at DAC in San Diego, CA. Hear what industry leaders from AMD, Juniper Networks, nVidia, Qualcomm and Xilinx had to say about using HSPICE and CustomSim in some of today’s most challenging designs.
Dirk Robinson, Analog Design Engineer, AMD; Nikhil Jayakumar, Design Engineer, Global Circuits Team, Juniper Networks; Wen-Hung Lo, Senior Mixed-Signal Design Engineer, NVIDIA; Mohamed Abu-Rahma, Staff Engineer, Memory Circuit Design Team, Qualcomm; Min-Fang Ho, CAD Manager, IC CAD, Xilinx


HSPICE SIG Video
HSPICE SIG: A Converging Analog World: Silicon, Package and System

On January 31, 2011, Synopsys hosted its first HSPICE SIG Event in Santa Clara, CA. At this event, industry leaders spoke about using HSPICE in some of today's most challenging designs.
Synopsys, Inc.



DAC 2009: Coping with Modern AMS Challenges

The guest panel of industry experts discussed how they are addressing key verification challenges at 32 nanometers, achieving high-accuracy verification for complex BCD and FPGA applications, and using power management techniques for custom DSP designs.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys; Aaron Barker, Staff Engineer, Sun Microsystems; Eugene Chen, CAD Director, Alter; Sandeep Tare, Verification Methodology Engineer, Texas Instruments; Lyes Djama, Smart Power Design Flows Manager; Pierluigi Daglio, AMS Design & Verification Flows Manager, STMicroelectronics



DAC 2009: Solutions for Tough Verification Challenges

Synopsys hosted a special VCS Verification Luncheon event at DAC in San Francisco, CA focused on the VCS functional verification solution. Verification R&D experts from leading companies discussed how they leverage VCS’s multicore performance, transaction-based verification, tight mixed-signal integration, comprehensive low power verification capabilities and proven methodologies to solve today’s toughest verification challenges.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys; YC Wong, Director of IC Engineering, Broadcom; Shrenik Mehta, Sr. Director of Frontend Tools and OpenSPARC, Sun Microsystems; Faisal Haque, Director of Engineering, Qualcomm; and Amit Chowdhry, Member of Technical Staff, AMD



VMM User Forum Lunch Event: ARM, Ltd.

Need for a Low Power Verification Methodology. Learn about ARM and Synopsys’ joint efforts to develop a Verification Methodology for Low Power Designs.
Alan Hunter, Verification Methodology Lead

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VMM User Forum Lunch Event: Renesas Technology Corporation

Low Power Verification User Experience See a presentation on the unique challenges of low power design verification and how they are being addressed by Reneses using Synopsys' tools.
Yoshio Inoue, Chief Engineer

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VMM User Forum Lunch Event: NVIDIA

Engineering the APX2500: Verification Methodology for Low Power Watch a presentation on NVIDIA’s experience using the Verification Methodology for Low Power Design on the APX2500, the world’s lowest power, high definition video and graphics computer on a chip.
Soma Bhattacharjee, Director of Engineering

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VMM User Forum Lunch Event: IBM

"Are We There Yet?" Listen to a discussion on VMM Planner and how IBM used it on their BIST project to determine when they had run enough random tests.
Nancy Pratt, BIST Verification Lead

PDF DOWNLOAD PRESENTATION (PDF)




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