Discovery 2009 

Frequently Asked Questions  

Q:What is being announced?
A:On April 6, 2009, Synopsys announced the latest version of its Discovery™ Verification Platform. Discovery 2009 includes new multicore verification performance, native design checks and comprehensive low-power verification capabilities. Accompanying this announcement, Synopsys announced the new CustomSim™ unified circuit simulator and new VCS® multicore verification technology.

Q:What is the Discovery Verification Platform?
A:The Discovery Verification Platform is Synopsys’ integrated AMS and functional verification solution. Discovery incorporates best-in-class technologies delivering high performance and scalability for digital and analog/mixed-signal (AMS) simulation. Discovery also includes debug, native design checks, assertions, low-power verification, verification intellectual property (IP), code and functional coverage, testbench automation and formal analysis.

Discovery supports industry-standard hardware design and verification languages, including SystemVerilog, Verilog, Verilog-AMS, VHDL, SystemC™, OpenVera®, IEEE 1801 (UPF), the VMM methodology and related VMM Applications. Discovery is part of the Synopsys Software-to-Silicon Verification Solution, the industry’s most comprehensive suite of proven embedded software development, system validation, functional verification and circuit simulation software, hardware, IP, methodologies and services for complex SoC design.

Q:What are the multicore capabilities provided with Discovery?
A:In March 2008, Synopsys announced its multicore initiative to deploy advanced parallel, threaded and other optimized compute technologies across its solutions. In the latest phase of this initiative, Synopsys is expanding VCS with multicore technology to speed up verification by 2x. Also, the new CustomSim unified circuit simulation solution includes multicore capabilities that deliver up to 4x speed-up.

Q:What are the native design checks provided in Discovery?
A:For many years, increasingly sophisticated static and dynamic checks have been available for digital designs in RTL. Static checks, such as those provided by Leda, VCS and MVRC, catch many design bugs quickly, without simulation or significant extra effort for the designer. With VCS, users can perform dynamic checks, using custom SystemVerilog assertions or VCS Assertion IP.

Verifying complex mixed-signal designs with sophisticated digitally controlled analog functions, multiple supply domains, and thousands of interface signals between the digital and analog blocks accurately is a major challenge. The traditional approach of using dynamic simulation alone may not be enough to ensure adequate coverage of the chip’s intended operations. CustomSim provides a comprehensive circuit simulation solution that includes static and dynamic native circuit checking to rapidly identify electrical rule violations and power management failures, thereby increasing designer productivity and confidence. CustomSim checks include power-down floating gates, missing level shifters, gate-oxide breakdown and forward-biased bulk diodes.

Q:What are the low-power verification capabilities provided with Discovery?
A:Discovery incorporates low-power verification capabilities at multiple levels of abstraction, from register-transfer level (RTL) to transistor level. VCS with MVSIM delivers true voltage-aware RTL and gate-level simulation, automated assertions, and comprehensive verification coverage, as defined in the recently published Verification Methodology Manual for Low Power (VMM-LP). CustomSim accurately verifies complex power management designs at the transistor level by identifying IR drop, electromigration and standby leakage issues that can impact the reliability and performance of integrated circuits.

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