Moore's Cores - Best Practices to Optimize Processor Cores for Performance, Power and Area Targets Specific to Your SoC
As silicon capacity continues to grow following Moore's law, so has the growth in computational power. This, along with the complexities of today's designs, has led to the need for multi-processor core SoC's to achieve design goals. Managing the complexity of designs that include CPUs, GPUs, and DSPs in a single chip can be quite challenging. Based upon years of Synopsys' consulting experience implementing hundreds of these SoC's, this webinar will outline design best practices and pitfalls to avoid, to enable you to achieve the right balance of high performance, low power and smaller area.
Jonathan Young, Director, Design Consulting, Synopsys
May 13, 2014
Micron Case Study: Electrical Modeling of 3D-IC Through-Silicon Vias Using HSPICE
Learn how to effectively model the impact of TSVs on signal and power delivery, especially for high-speed applications.
Fuad Badrieh, Ph.D., Principal Engineer, Micron Technology; Hany Elhak, Product Marketing Manager, Synopsys
Jul 10, 2013
Enabling 3D-IC Integration
Hear how Xilinx is using SSI technology to deliver higher levels of integration and flexibility in FPGA products, and learn how Synopsys' silicon-proven tools are enabling 3D-IC integration.
Steve Smith, Senior Director, 3D-IC Strategy and Marketing, Synopsys; Shankar Lakka, Director of IC Design, Full-Chip FPGA Integration Group, Xilinx
Jul 18, 2012