3D IC Solutions FAQ 


Q:What is Synopsys announcing?
A:Synopsys is announcing an initiative to accelerate the design of stacked multiple-die silicon systems using 3D-IC integration. As part of this initiative, Synopsys is delivering a comprehensive EDA solution, including enhanced versions of its IC implementation and circuit simulation products.

Q:What is 3D-IC integration?
A:3D-IC integration complements conventional transistor scaling to enable designers to achieve higher levels of integration by allowing multiple die to be stacked vertically, or in a side-by-side “2.5D” configuration on a silicon interposer. 3D-IC integration uses through-silicon via (TSV) technology, an emerging interconnection technology that may eventually replace the traditional wire-bonding process in chip/wafer stacking.

Q:What are the benefits of 3D-IC integration?
A:3D-IC integration offers benefits for design teams looking to boost system performance, reduce form factor and lower power consumption. Further, 3D-IC integration can support the combination of highly heterogeneous process technologies, thus enabling the lifespan of mature semiconductor process technologies to be extended with resulting cost savings and accelerated time-to-market advantages.

Q:Where can 3D-IC integration be deployed?
A:3D-IC integration is being deployed in many application domains, such as high-capacity FPGAs, high-density memory stacks, as well as advanced mobile and consumer applications that require multiple semiconductor technologies packaged together in a small, power-efficient and cost-effective manner.

Q:What are the tools incorporated into the Synopsys 3D-IC solution?
A:Synopsys' 3D-IC solution incorporates many tools:
  • DFTMAX™ test automation: design-for-test for stacked die and TSV
  • DesignWare® STAR Memory System® IP: integrated memory test, diagnostic and repair solution
  • IC Compiler: place-and-route support, including TSV, microbump, silicon interposer redistribution layer (RDL) and signal routing, power mesh creation and interconnect checks
  • StarRC™ Ultra parasitic extraction: support for TSV, microbump, interposer RDL and signal routing metal
  • HSPICE® and CustomSim™ circuit simulation: multi-die interconnect analysis
  • PrimeRail: IR-drop and EM analysis
  • IC Validator: DRC for microbumps and TSVs, LVS connectivity checking between stacked die
  • Galaxy Custom Designer® implementation solution: specialized custom edits to silicon interposer RDL, signal routing and power mesh
  • Sentaurus Interconnect: thermo-mechanical stress analysis to evaluate the impact of TSVs and microbumps used in multi-die stacks

Q:What are the benefits of the Synopsys 3D-IC solution?
A:Synopsys is working closely with leading IC design and manufacturing companies to deliver a comprehensive EDA solution for 3D-IC design. By incorporating advanced solutions that meet the needs of these early users of 3D-IC integration technologies into its IC implementation and analysis tools, Synopsys is enabling the broader design community to implement stacked multi-die systems faster and with lower risk.

Q:How are the Synopsys EDA tools enhanced to support 3D-IC integration?
A:Many Synopsys IC implementation and analysis tools are enhanced to recognize the additional manufacturing technologies required for 3D-IC integration. For example, the StarRC Ultra parasitic extraction tool provides a method to describe the dimensions and materials used to create TSVs and additional interconnect routing layers, such as redistribution layers (RDL). For the physical implementation of ICs used in 3D-IC integration systems, IC Compiler supports the placement and routing of TSVs, and is enhanced to support new manufacturing rules for I/O pads and RDL routing of silicon interposers and stacked die. For design rule checking (DRC) and layout vs. schematic (LVS) checking, the IC Validator physical verification tool supports additional rules to enable correct manufacturing of 3D-IC integration designs. HSPICE and CustomSim circuit simulators support multiple technologies within the same netlist to enable concurrent analysis of the interconnect between multiple die in a 3D-IC integration design.

Q:What does Synopsys offer to explore the potential impact of using 3D-IC integration technologies on silicon performance and reliability?
A:Multi-die stacks incorporate different materials, often bonded together, with varying coefficients of thermal expansion (CTE). Any temperature change causes material stress due to thermal mismatch, leading to silicon deformation and affecting transistor performance. Furthermore, TSVs, microbumps and other solder bumps produce a permanent stress in the zone around them. Synopsys’ Sentaurus Interconnect TCAD tool analyzes these effects and models the TSVs in the die stacks, enabling performance and reliability optimization. Semiconductor companies use TCAD modeling results to create design rules specific to 3D-IC integration to ensure design performance, manufacturability and reliability.

Q:How do I get more information about the Synopsys 3D-IC solution?
A:For more information, please visit the Synopsys 3D-IC website: www.synopsys.com/3D-IC.