Design Challenges
The 20nm process node poses significant design and manufacturing challenges that impact the EDA tools.
- Complex Double Patterning lithography requirements:
- Rule-aware placement and routing to ensure ability to color masks correctly and efficiently
- In-Design physical verification throughout the flow to reduce time-consuming, uncertain iterations
- Accurate higher levels of extraction and timing analysis to allow for manufacturing variability
- Performance and capacity requirements for the next generation designs which require much higher levels of tool interoperability, high degrees of multi-core processing and an integrated design environment to maximize design productivity in particular:
- Early RTL and design exploration
- Physical guidance from synthesis to implementation tools
- Digital and Custom co-design
- In-Design physical verification with implementation
- Tightly coupled signoff and implementation tools
- ECO guidance capabilities
The 20nm process node will enable designs to run at 2GHz+ operating frequency. To achieve this, improved modeling, enhanced guidance and analysis, tools and high degrees of predictability throughout the design flow will be required.
Foundry Partners and ConsortiumsSynopsys is actively working with leading 20nm foundries, consortiums and eco-system partners to address the significant challenges with the 20nm process node. This results in availability of foundry certified solutions in the shortest possible time.