Accelerating 20nm Double Patterning Verification
This whitepaper presents the key concepts of DPT compliant design and demonstrates how new signoff technology in IC Validator makes it possible to ensure 20nm manufacturing compliance. Recognizing that the designer productivity necessary cannot be achieved alone by point-tool enhancements and post-processing techniques, the paper outlines advances in In-Design physical verification within IC Compiler.
Paul Friedberg, CAE, Synopsys; Stelios Diamantidis, Product Marketing, Synopsys

20nm and Beyond white paper
The consumer’s insatiable demand for greater performance, a shrinking form factor and extended battery life, all while continuing the trend for lower end user cost is the driving force behind the semiconductor industry’s rapid evolution to ever smaller process geometries.
Andy Biddle, Product Marketing Manager, Galaxy Implementation Platform, Synopsys