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2014 SNUG Silicon Valley
A Pragmatic Approach to Layering Protocol Verification Using UVM
Layering protocols are modeled using layering structures that mirror the protocol layers. There are significant challenges in modeling verification components for layering protocols including reuse, scalability, controllability and observability. In this paper, a pragmatic approach using Universal Verification Methodology for layering protocol verification is presented to address these challenges.
Rahul Chauhan & Gurpreet Kaire, Broadcom Inc.; Ravindra Ganti & Subhranil Deb, Synopsys Inc.

2014 SNUG China
Using IC Compiler Custom Co-Design to Meet High-Speed DDR Timing Requirement (Mandarin)
For high-speed DDR design, how to manage skew between PHYAC/PHYDATX8 and SSTL I/O signals has become critical. This paper describes how to use IC Compiler Custom Co-Design to minimize signal skew to meet your design specification requirements.
Feng Xiang & Xiu-Yu Xu, China Glarun Technology; Zhun Cai, Synopsys Inc.

An Efficient Way of Optimizing Leakage Power Under MCMM (Mandarin)
For advanced processes below 65nm, chip designers face a huge challenge to reduce timing closure runtime while concurrently optimizing chip leakage power. This paper introduces an efficient way to dramatically speed timing closure and optimize leakage power using new PrimeTime ECO leakage fixing capability for MCMM-based analysis.
Xio-Fei Liu & Tian-Ming Yan, Suzhou CAS Integrate Circuit Design Center; Zhun Cai, Synopsys Inc.

2013 SNUG Silicon Valley
A Power-Centric Timing Optimization Flow for a Quad-Core ARM Cortex-A7 Processor
The ARM Cortex-A7 MPCore™ Processor - Introducing big.LITTLE™ Processing Implementation Optimization for big.LITTLE through ARM-Synopsys Collaboration
Bernard Ortiz de Montellano, ARM; Dale Lomelino, Synopsys

Engineering Trade-offs in the Implementation of a High Performance ARM® Cortex™-A15 Dual Core Processor
The ARM® Cortex™-A15 MPCore™ Processor - Implementation Optimization for the "big" core in a big.LITTLE SoC
Bernard Ortiz de Montellano, ARM; Joe Walston, Synopsys

2013 SNUG France
Concurrent Top and Blocks Level Implementation of a High Performance Graphics Core Using One-Pass Timing Closure in Synopsys IC Compiler
Implementing a High Performance Graphics Core with complex low-power features and several operating points in an advanced design node (28nm FDSOI) challenges the traditional Place and Route flow. Adding a very short schedule and improving the resource utilization for the execution of this multi-millions instances design through a Hierarchical Physical Implementation is asking for an innovative one pass timing closure flow. This article will describe how, using IC Compiler (ICC) through a top-down approach and concurrent top and blocks implementation methodology, the target frequency, the power constraints and the schedule can be achieved successfully. From the Design Planning stage to the Signoff, we will tackle the following aspects in ICC: usage of Black-Boxes for early Design Planning, Budgeting and advanced Placement and Optimization, targeting PrimeTime SI Signoff for final ECO, with specific considerations on the SDC blocks budgets and QTM models handling.
Corine Pulvermuller & Julien Guillemain, STMicroelectronics

2012 SNUG Silicon Valley
Slow Dancing with Memories - Sometimes it's Harder to go Slow
Usually we try to make FPGA rapid prototyping run as fast as possible, but sometimes it needs to go slow, and sometimes this can be a real problem. For a design that is supposed to run at 800 MHz and supposed to interface with SDRAM at 667 MHz, to run in an FPGA at 25 MHz and interface with memory at 50 MHz, seems impossible. But, it can be done! This paper presents a cookbook approach to making it work and includes a simple reference design that proves it is possible.
Manoj Agarwal & David Castle, SanDisk

2011 SNUG Europe
CHIPS and iPEAS: It's not Mushy
Drawing on many years of SoC design experience and more than 50 tape-outs from Synopsys Professional Services this paper describes these challenges, their solutions and what to look out for when selecting and designing with IP.
Jon Young, Synopsys Professional Services

2011 VLSI Design
Design methodologies and techniques for production low power SOC designs
Dynamic Voltage Frequency Scaling; Power-gating design; Production low-power SOC implementation; Power intent definitions through UPF; Production low-power design environment; Summary
Dr. Kaijian Shi

2010 DAC
Selection and Integration of a Signal Processing Package for a SystemVerilog/VMM Verification Environment
A SystemVerilog/VMM verification environment for a DSP based SOC is described. This environment uses an open source C++ library for signal processing functions. The criteria used for selecting the verification environment architecture is detailed. The environment implementation, merits and tradeoffs are discussed.
Matt Spaethe, Motorola Inc., Wes Kirk, Motorola Inc., Ron Shipp, Synopsys Inc.

2010 IEEE SOCC
Low-power SOC implementation: What you need to know
Dynamic Voltage Frequency Scaling; Power-gating design; Production low-power SOC implementation; Power intent definitions through UPF; Production low-power design environment; Summary
Dr. Kaijian Shi, Synopsys Professional Services

2009 SNUG UK
Implementation Methodology for Dual-Mode GPS Receiver
GPS functionality has been synonymous with in-car navigation but has recently emerged as a must-have feature in recent cellphones such as the Apple iPhone, Blackberry Pearl and Nokia N95. These are examples of embedded positioning, capable of enabling features and functionality in a wide range of additional portable electronics such as digital cameras, watches and media players.
Tom Ryan, Synopsys Professional Services; Jon Young, Synopsys Professional Services; Chris Atkinson, Synopsys Professional Services; David Tester, CTO, Air.

2009 DesignCon
Power Gating Design Tradeoffs and Considerations In Production Low-Power Designs
This paper explains in details various overheads and tradeoffs in the power-gating designs. It also provides design considerations and guidelines for production power-gating design based on extensive power-gating design experience and in-depth understanding of the nature of the power-gating design.
Kaijin Shi, Synopsys Professional Services; David Flynn, ARM, Ltd.

2008 SNUG San Jose
Implementing Multi-VDD Designs with DCT and ICC
Consumer electronics is a key driver for many IC designs today. There are several different techniques available to help reduce an IC’s power consumption including – Multi-VT libraries, advance CTS techniques such as clock gating and FF clustering, dynamic power reduction algorithms that are built in to EDA tools, and multi-voltage design (MVDD). This paper explores these power reduction techniques and how to apply them using specific flow, tool and methodology examples.
Chad Gamble, Synopsys Professional Services

Randomized Testbench Development, a Case Study in USB
USB devices contain mandatory functionality as specified by the USB specification and up to sixteen bidirectional data pipes. USB hubs repeat traffic and allow up to 127 devices to be connected in a single tree. Complete USB trees are difficult to test because of the large state space and the inter-dependent data relationships.
Jason Remple, Broadcom Denis Bussaglia, Synopsys Professional Services Frederic Krampac, Synopsys Professional Services

2007 SNUG San Jose
Physical Design and Timing Challenges of a Serial PHY
In recent years, high-speed serial links (SERDES) have become popular. In the personal computer market, examples include PCI-Express (2.5Gbps) and SATA 2 (1.5-3Gbps). Furthermore, XAUI (3.125Gps) has gained popularity as an ASIC interface. This chapter covers the physical layer, multi-protocol IP (PHY) that handles the aforementioned protocols. While the analog physical design was challenging, so too was the digital physical design. Select digital physical design and timing closure techniques are covered in this chapter. These techniques give insight into challenges faced by a PHY IP provider to develop a high-performance and configurable PHY.
Ken Umino, Synopsys Professional Services Steve Everley, Everley Consulting Ross Segelken, Synopsys Jason Upton, Synopsys John Stonick, Synopsys

Core Based Test using Scan Compression and Core Isolation
Scaling technology and increasing design size are continued to pose challenge for test. Test data volume and power consumption (IR drop and dynamic power) during test have made it impossible to test the whole design at once. One of the most effective ways to address the issue is to use “divide and conquer” approach. A core based test strategy with scan compression (DFTMAX) technique is presented to overcome the test data volume and the power consumption during test concerns. To cater to various test needs (multi-site testing, chip-level integration etc.), multi-mode test architecture is implemented.
Sandeep Kaushik, Synopsys Professional Services Paul Policke, Qualcomm

Decoupling Capacitance Estimation, Implementation and Verification: A Practical Approach for Deep Submicron SoCs
The problem of dynamic variations in supply voltage and the related impact on chip performance is a major issue facing today's DSM SoC design teams. Through careful design of the power supply network, correct chip functionality can be ensured.
David Stringfellow, Synopsys Professional Services John Pedicone, Synopsys Professional Services

Advantages of Driving DDR Interface Logic at 2x the DDR Clock versus 1x the DDR Clock
Double data rate (DDR) designs have become common in many interfaces and many ASICs. DDR uses both edges of a clock to transfer data so that it has twice the throughput of a single data rate (SDR) application at the same frequency. In a 1x clock DDR design, the clock driving the interface logic and the DDR clock are the same frequency, while with 2x clock DDR the clocking is twice the DDR clock. This paper covers the compares the designs, timing constraints, and timing differences of real design examples, and shows that 2x clock DDR has significant advantages.
Ken Umino, Synopsys Professional Services Pete Thoeming, Thomson Silicon Components

Applying CRV to Microprocessor Verification
Many processors have been and continue to be verified using directed tests. As processors become increasingly complex, language features such as the SystemVerilog random sequence generator have helped verification engineers to create random instruction sequences to improve the quality of the stimulus, but they are procedural and do not take full advantage of object-based randomization using constraints.
Jason Chen, Synopsys Professional Services

2007 SNUG Boston
Hold Me Please! How to Fix Post-Route Hold Violations Quickly and Easily Using Distributed Multi-Scenario Analysis
Creating an ECO to fix hold violations can be time-consuming. If a designer tries to determine interactively the changes required, they must first define the changes for one PVT corner, then confirm that the changes do not create new setup or hold violations in other corners. If there are multiple timing modes, all timing modes must be checked as well to confirm that no new violations arise. If a violation shows up in another corner or mode, the change must be updated and verified for all scenarios again.
Dwight Galbi, Analog Devices, Inc.; Beth Herman, Synopsys Professional Services; Brandon Waldo, Synopsys Professional Services; Mike Castellano, Synopsys Professional Services; Christopher Papdemetrious, Synopsys, Inc.

Finding A Tricky IP Bug with SystemVerilog Assertions (A Real World Example)
There are many SVA tutorials and getting started papers, but this is the real thing, successfully using SystemVerilog Assertions to find a bug in third-party IP and helping the designer fix the problem. This paper shows how Synopsys Professional Services proved that a data-corruption problem in a bus-to-bus bridge IP—that plagued us while verifying a complex SOC—was a real bug. It presents the SVA used to pinpoint the bug and report it to the vendor, which resulted in a very quick fix. And, it introduces the concepts, so you can do the same thing.
David E. Castle, Synopsys Professional Services Paul McGaugh, Broad Reach Engineering, Inc.

IR-drop analysis of a UDSM complex power-gating design
Full chip static and dynamic IR-drop analysis becomes a signoff necessity for power integrity of ultra-deep sub-micron (UDSM) technology based designs such as 65nm and below. There are various challenges in the IR-drop analysis at chip level due to the size of the design and the complexities in dealing with various design components such as soft and hard macros.
Kaijian Shi, Synopsys Professional Services Julio C. Hernandez, Synopsys Professional Services Michael Allen, Analog Devices, Inc. Dwight Galbi, Analog Devices, Inc. Joe Geisler, Analog Devices, Inc.

Multiphase Flow for Meeting Metal Density and Gradient Requirements at 65nm
In this paper we will describe a three phase flow that was developed by ADI and Synopsys Professional Services to satisfy 65nm metal density and metal density gradient requirements with minimal impact on timing. The first phase consists of a three-pass flow using IC compiler with different polygon and timing parameters used to fill the chip core area. The second phase is a Hercules based OD and POLY fill across the full chip and metal fill only over the pad ring. The third phase is a multi-pass, area-based run to address specific metal density gradient design rule violations reported by Hercules DRC.
Jim Dodrill, Analog Devices Inc.; Dwight Galbi, Analog Devices Inc.; Moheb Basta, Synopsys Professional Services; Mike Castellano, Synopsys Professional Services

Advanced Low Power, Multi-Supply Implementation Techniques for 65nm and Beyond using DCT and ICC
Designing low-power ASICs in the nanometer era using 65nm and beyond can be complex. With leakage power becoming more dominant as the process technology shrinks, more methods to reduce idle power need to be used. Multi-supply designs with power-down blocks allow for large reductions in leakage power with the trade-off of design complexity.
Dwight Galbi, Analog Devices, Inc. Brandon Waldo, Synopsys Professional Services

2007 Radiation Hardened Electronics Technology (RHET)
Designing Advanced ASIC’s with Synopsys Design Tool Suite
Synopsys Professional Services' experienced design consultants are at the fore-front of design, as evidenced by their contribution to these published Technical Papers and Presentations. Our objective is to share these papers with our customers and prospective customers in order to help achieve success on their own projects.
Rick Hayden, Synopsys Professional Services

2007 IEEE SoC
A Wakeup Rush Current and Charge-up Time Analysis Method for Programmable Power Gating Designs
Programmable power-gating structure is often implemented in advance low-power designs where switch cells are connected into a number of separate daisy chains which can be configured into a trickle charge chain and a main chain. The main chain can also be programmed with desired turn-on time to achieve short charge-up time while meeting max rush current constraints during wakeup.
Kaijin Shi, Synopsys Professional Services Jingsong Li, Synopsys, Inc.

2007 DesignCon
Power Network Synthesis of Power Gating Designs
This paper describes a new power network synthesis method for power-gating designs where sleep transistors are implemented connecting permanent and virtual power networks. Differing from other methods, the new method addressed the requirements from industrial power-gating designs. In industrial power-gating designs, the sleep transistors are custom designed with a fixed size.
Kaijian Shi, Synopsys Professional Services Zhian Lin, Synopsys Yi-Min Jiang, Synopsys

Comparison of a 1x Clock DDR Design Versus a 2x Clock DDR Design
Double data rate (DDR) designs have become common in many interfaces and many ASICs. DDR uses both edges of a clock to transfer data so that it has twice the throughput of a single data rate (SDR) application at the same frequency. In a 1x clock DDR design, the clock driving the interface logic and the DDR clock are the same frequency. In a 2x clock DDR design, the clock driving the interface logic is twice the frequency of the DDR clock. This paper covers the comparison between a 1x clock DDR design versus a 2x clock DDR design.
Ken Umino, Synopsys Professional Services Peter Thoeming, Thomson Silicon Components

2006 The World Congress in Computer Science
PSeuDoFFIL: Power Saving Datapath FiFo Insertion Logic
A technique is described to dynamically limit power dissipation in heavily pipelined digital circuits. Stages in the pipeline are clock gated based upon validity of data at that stage. As the pipe approaches a stalled or inactive state, branches of the clock tree are progressively disabled stage by stage. The technique has the additional advantage of removing gaps or “bubbles” in the data streams, improving the latency of the system.
Josefina Hobbs, Synopsys Worldwide Application Services, John McCardle, ATI, John Lofgren, Synopsys Solutions Group

2006 SNUG San Jose
Integrating System Models into an RVM Environment
As designs increase with complexity, the state space in which designs must be verified has grown to a level that cannot be properly managed using directed methods. A constrained random approach that leverages RVM offers a method for providing a large amount of valid test cases that yield a high level of functional coverage.
Anand Acharya, Qualcomm Shaun Evans, Synopsys Professional Services

1.2 – 1.5 + M instances flat design for 0.13um process
This paper will highlight the benefits of using a flat design methodology for place and route. The technical challenges of a flat design methodology will be addressed on a 1.2 – 1.5 Million instances design in a .13um TSMC process. Using a flat design methodology might help to improve turn around time (TAT) and the quality of results (QOR) in the area of timing closure related to block sizing, cross-talk between blocks, and time budgeting in blocks.
Steve Doan, Synopsys Inc. Koshi Matsushita, Synopsys Inc. Chien-yeh Wu, Synopsys Inc. Srini Burugu, Synopsys Inc.

Automated FFT RTL creation using Verilog with Matlab and Perl
Digital signal processing often requires FFT signal processing. The variables are the mathematical precision, using either floating point or fixed point computations, and the number of FFT points required. The design can either be done flat with parallel FFT butterflies, or serially with a single butterfly, or in some cases a mix between a completely flat and serial butterfly using more than one butterfly but a subset of total butterflies.
Richard Hayden , Synopsys Professional Services Cole O’Berry, Synopsys Professional Services John Kuhns , Synopsys Professional Services

2006 SNUG Europe
Library Gotchas Guidelines to Physical Library Qualification
Have you ever closed timing in Physical Compiler only to realize that your timing is way off in Astro because the units defined in the plib did not match the units defined in Astro technology file? Did physical verification fail two days before the deadline causing you “tapeout frenzies” because the third party IP inside your block was not LVS/DRC clean? If you have experienced anything similar, you are not alone.
Lavanya Murugesan, Synopsys, Inc., Tamiko Yoneyama, Synopsys, Inc., Koshi Matsushita, Synopsys, Inc.

An efficient script-based RTL-to-GDSII flow using the Jupiter-XT - PC - Astro tool chain in 130 nm on a 350K-instance design
The integration of complex circuits on silicon has been known for long to require longer schedules than FPGA prototyping because of the complexity of silicon processes and the variations and inaccuracies to take into account. But with the most recent generation of physical implementation tools which ensure a better prediction and correlation between the successive design phases than before, it has now become feasible to integrate multi-million transistors circuits within an aggressive time frame.
Pierre-Marie Signe, Abilis Systems John Lofgren, Synopsys Professional Services, Synopys Inc.

SPIRIT-based IP Assembly and SDC promotion for a 65nm System-on-Chip using coreAssembler
To cope with the huge time-to-market pressure, every designer is looking at a “plug-and-play” solution to build complex System-on-Chips. One of the current challenges of such designs is to assemble quickly and consistently a high numbers of IPs around one or more on-chip-bus. Thanks to SPIRIT, Synopsys coreTools & ST Microelectronics design data structures, this process can be made much more efficient.
Sal Tiralongo, Synopsys Professional Services, Synopys Inc. Stephane Maulet, Synopsys Professional Services, Synopys Inc. Emanuele Irrera, Synopsys Professional Services, Synopys Inc.

Rectilinear Supply Mesh Insertion using JupiterXT Virtual Flat Flow
Building ARM’s fastest and most power-efficient microprocessor required the use of multiple supply domains at the core level. ARM took advantage of the features within the Synopsys’ JupiterXT Virtual Flat tool to partition the supply domains into rectilinear shapes for mesh insertion. While the design is still flat, the native functions for inserting supply on these rectilinear partitions are limited to a rectangular shape.
Abid M. Jindani, Synopsys Professional Services, Synopys Inc. Stephanie Miller, ARM Inc.

2006 SNUG Boston
Methodology to Analyze and Insert a Power Mesh Early in Design Cycle
An IC design engineer is often required to perform design related tasks early in the design phase before all necessary data is present. For example, a designer may be asked to explore power mesh design and analysis before all IP is procured or RTL is complete. The designer may have rough targets for die size, maximum power consumption, and maximum IR drop. Rather than wait, power mesh design and analysis could be started with this early data. This paper covers a methodology to analyze a power mesh using a dummy netlist consisting of 1000 buffers, and then proposes a procedure that inserts a power mesh properly aligned with the routing grid.
Joseph Schrand, Thomson Silicon Components Ken Umino, Synopsys Professional Services Evan Chen, Synopsys Professional Services

Technique for Optimizing IBM Power PC 440 Cache
In the IBM PowerPC 440 Core, both the setup and access paths of the cache SRAMs are in the critical path; but, depending on timing, one or the other is more critical. It is possible to balance the clock latency to these SRAMs—similar to latch time-borrowing—to minimize the negative slack on both the input and output paths. Choosing the appropriate clock latency for each SRAM is a very important step in this process.
David E. Castle, Synopsys Professional Services; Vijay Gullipalli, Synopsys Professional Services; Paul McGaugh, Broad Reach Engineering, Inc.

Automated Response Generation for IP Based Subsystem Verification
This paper describes a method for producing automated constrained random responses to write and read requests in support of functional verification of an IP based subsystem. This approach, as employed by Synopsys Professional Services, can reduce the overall effort expended on verification by enabling full use of constrained random verification techniques. This method yields high productivity by enabling test writers to focus on constrained random stimulus development rather than manually creating response scenarios.
Tony Ezell, Synopsys Professional Services

2006 IEEE VLSI-DAT Taiwan
Sleep Transistor Design and Implementation – Simple Concepts Yet Challenges To Be Optimum
Optimum sleep transistor design and implementation are critical to a successful power-gating design. This paper describes a number of critical considerations for the sleep transistor design and implementation including header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency.
Kaijian Shi, Synopsys, Inc. David Howard ARM, Ltd.

Power-On Current Control In Sleep Transistor Implementations
Various current control techniques are described to limit current surge when sleep transistor are turned on to power a design. Advantages and disadvantages in the techniques are also discussed. The trade-off consideration on power-on latency adds more challenges in the current control in sleep transistor implementations which are addressed in the paper.
Kaijian Shi, Synopsys, Inc. David Howard ARM, Ltd.

2006 GSPx
Physical Design Techniques of a Multi-Protocol Serdes Phy
In recent years, high-speed serial links (SERDES) have become popular. In the personal computer market, examples include PCI-Express (2.5Gbps) and SATA (1.5-3Gbps). Furthermore, XAUI (3.125Gps) has gained popularity as an ASIC interface. This paper covers a physical layer, multi-protocol IP (PHY) that handles the aforementioned protocols.
Ken Umino, Synopsys Professional Services Jason Upton, Synopsys Ross Segelken, Synopsys John Stonick, Synopsys

2006 DesignCon
Back-End Methodology and Techniques for a Multi-Protocol Mixed Signal IP Design
ASIC I/Os have been evolving from relatively slow parallel interfaces to high-speed serial links. Examples include PCI to PCI Express (2.5Gbps), ATA to SATA (1.5-3Gbps), and SCSI to SAS (1.5-3Gbps). Additionally, the XAUI interface, which operates at 3.125Gb/s, has gained popularity as an ASIC interface. This evolution has created a difficult design problem for ASIC manufacturers that is increasingly being solved by purchasing rather than developing the required I/O IP.
Ken Umino, Synopsys Inc. Professional Services Jason Upton, Synopsys Inc. Solutions Group John Stonick, Synopsys Inc. Solutions Group Ross Segelken, Synopsys Inc. Solutions Group Bill Beale, Synopsys Inc. Solutions Group

2006 DAC
Challenges in Sleep Transistor Design and Implementation in Low-Power Designs
Optimum power gating sleep transistor design and implementation are critical to a successful low-power design. This paper describes important considerations for the sleep transistor design and implementation including header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency. It also investigated various power-on current rush control methods for the sleep transistor implementation.
Kaijian Shi, Synopsys Professional Services, David Howard, ARM Ltd.



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