SoC Integration & Verification 

 
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Synopsys design consultants have the expertise and experience to assist you in every stage of SoC design. This includes design feasibility and performance estimates, SoC configuration, integration and verification. We work directly with system-level designers to ensure that design specifications accurately capture design intent at both the block and chip levels, helping to minimize iterations between the architecture and RTL implementation. We can then assist your team in translating the SoC specification into a high-quality RTL description following best practices pioneered by Synopsys.

SoC Integration
The growing number and complexity of IP blocks and subsystems in today's SoC designs challenge even the most experienced design teams, especially when the IP is based on a protocol that is new or otherwise unfamiliar to the team. The quality of the configuration and integration of complex IP blocks can have a significant impact on a SoC's development schedule and performance. Synopsys design consultants are skilled in SoC configuration and integration, and possess extensive knowledge of DesignWare Interface IP.

Synopsys' SoC integration services include assistance with:
  • Design feasibility, analyzing power, performance, area, complexity, design effort, risks, etc.
  • Creating functional specifications based on design requirements
  • Building, configuring and integrating complex IP blocks and subsystems, including controller and PHY integration for protocols such as USB, PCI Express, DDR, HDMI and SATA.
  • DesignWare IP and processor core hardening
  • Top-level SoC integration

SoC Verification
Verification remains the most significant bottleneck in getting advanced SoCs to market. Traditional verification methods cannot scale with today's chip complexity. The development of an independent verification plan, protocol expertise, and efficient use of verification IP (VIP) are keys to minimizing functional bugs. Synopsys verification experts help you take advantage of advanced techniques such as assertions, constrained-random stimulus generation, and coverage-driven test generation and rapidly deploy them across your project teams.

Our consultants share expertise with Synopsys' Discovery™ Verification Platform tools and apply best practices based on proven methodologies such as UVM and VMM for SystemVerilog. Creating a design environment with UVM- or VMM-compliant building blocks takes less time, eases cross-site collaboration and maximizes test bench re-use for future projects.

Synopsys' SoC verification services include assistance with:
  • Verification planning including architecture for re-use
  • Deploying advanced verification methodologies such as UVM or VMM
  • Testbench generation
  • Integration of protocol-specific VIP

To get more information on how we can customize our services for you, please contact Synopsys Professional Services or call your local sales representative.



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