Technical Papers 2005 

Conference Papers and Presentations 

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IEEE SOCC 2005
This paper described timing perspective challenges in PowerPC440 soft core development and provided solutions. Various micro architectures and memory implementations have been explored, and physical synthesis strategies and clock skew management have been developed to meet the challenging speed target.
Terry Biggs, Ken Umino and Kaijian Shi,Synopsys Professional Services, Synopsys Inc.
IP SoC 2005
This paper describes an innovative methodology that makes use of XML-based IP descriptions, including constraints information, to produce automatically synthesis, STA and formal verification tool scripts for sub-systems. The XML information can be considered to be a ‘machine readable, electronic data book’.
Denis Bussaglia, Synopsys Professional Services
Marino Strik, Philips Semiconductors
Mark Noll, Synopsys Solutions Group
Geoff Mole, Philips Semiconductors
Ralf Gaisbauer, Philips Semiconductors
Hans Peter van Lohuizen, Philips Semiconductors
SNUG Boston 2005
Transactors are testbench components whose primary responsibility is processing transactions. As the transactors are typically encapsulated in a verification environment that is shared amongst tests, it is important to design the transactors such that they offer flexibility and extensibility to meet the individual test requirements. Transactor callback methods are powerful ways to provide hooks or access points for the users (such as the tests) of the transactors to intervene, modify, or augment transactor behaviors without changing any transactor code – a true form of transactor reuse.
John Zook, StarGen Inc.
Jason C. Chen, Synopsys Professional Services

This paper describes a method for inserting DL (Data Link Layer) and Phy (Physical Layer) errors in support of functional verification of a multi-function PCIe (PCI Express) bridge chip. This approach, when combined with Transaction Layer reference models can reduce the overall effort expended on verification by enabling full use of constrained random verification techniques. We show a way to automate code writing to produce DL and Phy errors. This enables test writers to focus on creating the best stimuli for exercising the rest of the chip, which yields high productivity.
Jim Sweeten, Stargen, Inc.
Tony Ezell, Synopsys Professional Services


In many deep sub-micron designs, IR drop can significantly impact the functionality so performing early IR drop and rise analysis studies can avoid surprises before the tapeout. The design of the power grid becomes even more challenging for smaller geometry (130nm and below) designs with wire-bond packages. In this paper we describe various techniques and tradeoffs we employed in designing the optimal power grid for a large die to meet a 10% IR drop specification using the Synopsys Astro-Rail tool. The goal was not only to achieve the IR drop spec but also to create a grid that gave the detail router more flexibility.
Srini Burugu, Sumeer Arya, Steve Doan, Synopsys Professional Services

The complexity of today's System On Chip (SoC) designs requires a faster and simpler flow and methodology for new SoC design projects. To get more SoCs to market faster and less expensively, STMicroelectronics combined forces with Synopsys® Professional Services to conceive a new flow and methodology for digital audio system platform.
Mauro Bosco, ST Microelectronics
Sam Bordbar, Synopsys Professional Services
Andreas Vielhaber, Synopsys, Inc


IEEE SOCC 2005
A Virtual Hierarchical design optimization method has been developed to combine strength of the flat and the hierarchical optimization methods for efficient and quality optimization of multi-million gate designs in a distributed computing environment. A novel design representation “Virtual Hierarchy” is proposed for subdesign optimization in a distributed computing environment. The principle and the implementation details of the method are described.
Thi Nguyen, Synopsys Inc.
Kaijian Shi, Synopsys Professional Services

This paper describes a novel clock isolation method that resolves issues in logical and physical synthesis caused by using clock as data to qualify signals or switch data flows in complex SoC designs. The principles of the method and implementation guidelines are described in detail. The advantages of the method include better quality-of-result of a design, fewer timing closure iterations and less complex design flow. The clock isolation method has been successfully implemented and verified in a complex SoC design.
Kaijian Shi, Synopsys Professional Services
Hichem Belhadj, Actel Co.

SNUG Taiwan 2005

Dave Scott and SachinIdgunji, Synopsys
Dar-Sun Tsien, Ph.D., UMC
Dave Flynn, ARM

SNUG China 2005
The use of AMBA-based buses is ubiquitous in today’s System On Chips (SoC). Verification IPs (VIP) are effective in generating stimuli for block-level, subsystem-level, and top-level testbenches. The reference verification methodology (RVM) and its base class library for Vera help verification engineers to build a testbench that enables constrained random verification and promotes re-use.
Prof. Yang Zhi Jia, Zhang Yu Feng, Li Su Gang, Shenyang Institute of Automation, Chinese Academy of Sciences
Jason C. Chen, Synopsys Professional Services

SNUG India 2005
Ever wished a "plug-and-play" solution to build a subsystem & deliver it within a week!! Thanks to Synopsys Core* Solution & ST Microelectronics IP infrastructure, this is now possible. As travel options have evolved from "bullock-cart" era to Supersonic, the same should reflect in IP packaging & SoC buildup arena. This is an obvious need considering time-to-market needs of SoCs.
Vivek Singh, Synopsys Professional Services
Preeti Rani, STMicroelectronics Ltd.,
Co-Authors:
Sanjeev Varshney, STMicroelectronics Ltd.,
Sal Tiralongo, Synopsys Professional Services
SNUG Europe 2005
Smaller micron geometries (0.13 um and below) bring with them new signal integrity challenges. The right approach depends both upon the nature of the design and the project goals. In this paper we describe several clock net implementation tradeoffs to be made for reaching timing closure: a) clock shielding vs. double-spacing, b) double-width wires vs. staying with single width, c) combinations of the shielding, double width and double spacing. Each of these can affect the project schedule and quality of results.
Sameer Nayar, PLX Technology Sumeer Arya, Srini Burugu, Brandon Waldo, Synopsys Professional Services

This paper presents an innovative methodology and platform to automate the architecture exploration, configuration, verification and implementation of a STBus1 based communication backbone for SoCs. In particular the paper will focus on the STBus System Verification Environment, based on Vera, and its integration within the “STBus GenKit”.
Giuseppe falconeri, Nizar Rhomdane, Houssem Bdioui, ST Microelectronics Sal Tiralongo, Nicolas Meunier, Synopsys Professional Services Francoise Casaubieilh, Synopsys Verification Group

Complex SoC designs often implemented various IPs and embedded memories. It is not uncommon that clocks are used as data to qualify signals in IPs, particularly legacy ones, and to switch address and data buses in dual access embedded memories which are popular in low-power designs. Using clock as data has created various issues in timing closure, particularly in logic and physical synthesis. To resolve the issue, a novel clock isolation method has been developed.
Hichem Belhadj Actel Co.
Kaijian Shi IP and Design Services, Synopsys Inc.

As the merits of dynamic frequency and voltage scaling for SoC energy efficiency are becoming more widely known, design teams are updating their methodologies to accommodate the requirements of variable supply voltage. Two of the most important methodology areas to consider are power planning and static timing analysis. A recent demonstration SoC shows how these parts of the design flow can be tailored to achieve significant power savings.
Dar-Sun Tsien, Ph.D. Sr. Director of Design Methodology, UMC
Dave Flynn ARM Fellow, ARM
Dave Scott and Sachin Idgunji Staff Design Consultants Synopsys Professional Services

SNUG San Jose 2005
With the increasing complexity of today’s deep submicron designs the need for identification of best practices and default methodologies becomes even greater; not so as to restrict the creativity of designers but to provide a context in which creativity can be exercised while ensuring that critical design issues are addressed.
Kevin Knapp and Chris Smith, Synopsys Professional Services

Layout parasitic extraction is a critical phase of today’s design flows. Smaller geometries require RC extraction tools which will accurately predict delays during simulation and timing analysis. Parasitic effects are becoming more prominent as gate geometries shrink to below 90 nm. The IBM Parasitic Extraction team at Essex Junction, Vermont is working closely with the Synopsys Professional Services team to develop and test technology files to enable the layout parasitic extraction of advanced processes for foundry customers. The purpose of this paper is to conduct a numerical analysis of various parasitic effects and to show how interconnect delay issues are magnified with shrinking process geometries.
Cole Zemke, IBM
Kevin Brelsford, WWAS, Synopsys, Inc.
Jitendra Lagu, Synopsys Professional Services

In many chip designs, there are usually multiple static timing analyses (STA) that must all pass timing before tape-out because there are usually multiple clock modes and process-voltagetemperature corners. At and below 130nm, signal integrity (SI) makes timing more challenging. Synopsys’ Galaxy tools, Physical Compiler and Astro, are proficient at fixing hold, max transition, max capacitance, and SI violations. However, these tools can work with only one clock mode and two corners, and have less then perfect correlation with the sign-off STA flow.
Atif Hussain, Texas Instruments
Ken Umino, Synopsys Professional Services

An ASIC with mixed signal IP content required signal analysis as part of the verification plan. The analysis was accomplished using MATLAB and SystemVerilog coupled through the DPI. This article describes the setup required to access the MATLAB engine library from SystemVerilog's DPI. The signal analysis which was performed using MATLAB is also covered, including steps made to support a self checking verification environment. Finally, while this project only needed the MATLAB engine library for analysis, some further applications of the coupling between SystemVerilog and MATLAB are considered.
Rene Abraham and Rabeek Mohamed, Midas Communications Technology, Inc.
Ron Shipp, Synopsys Professional Services

Design teams have developed manual approaches to estimating power and designing power networks for their SoCs. Typically, the team combines library vendor and fab vendor design guidelines with engineering estimation and floorplanning to produce robust strap-based and mesh-based power networks.
Hamid Piroozi, Krishna Gopinathannair, Thomson, Inc.
Ted Bernard and David Stringfellow, Synopsys Professional Services

In many designs excessive rail voltage drop can negatively impact the performance and, in some cases, the functionality of the device. The IR voltage drop or ground bounce can be reduced through the proper design of the power grid and by increasing the number of VDD and VSS pins. Determining the feasibility of a power grid design to meet required IR drop specifications and determining the correct number of pins may require early analysis, sometime even prior to basic design data availability.
Kenneth Egan, X-EMI, Inc.
Hani Saleh, Synopsys Professional Services



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