Tapeout Assistance 

Dedicated expertise to resolve tapeout bottlenecks 
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At-A-Glance
  • Specialists help to quickly resolve design and tool bottlenecks through tapeout
  • Implement new methodologies as needed
  • Dedicated physical design assistance when you need it most

Overview
The path to a successful tapeout is often lined with challenges that only become critical late in the design cycle. Some of these bottlenecks are predictable, others are not. In virtually all cases, delays in these final stages of the project are highly stressful and equally visible, as the project team pushes hard towards a successful tapeout. Synopsys Tapeout Assistance services help design teams in this critical stage of their project cycles. Physical design consultants provide dedicated support to help mitigate technical risks and address design and tools issues that are hindering tapeout. The Synopsys on-site staff is backed by a worldwide network of consulting, CAE and R&D resources.

Tapeout Assist Fig1

Figure 1: Specialists assist your project team in the most critical phases of
physical design to facilitate tapeout.

Synopsys consultants understand the issues that most commonly impede progress in the physical design phase – from constraints management to power distribution and clocking to DRC/LVS integration issues – and possess the expertise and experience to develop practical action plans with your design team. While the primary objective is completing your current design project, our Tapeout Assistance services often lead to flow and methodology enhancements as well as knowledge transfer that improve your team's readiness for the next tapeout.

Synopsys consultants deliver tool and implementation assistance in important areas that often cause delays in the latter stages of a design project, including:
  • Constraints management at block and chip level
  • Floorplan macro placement optimization
    • Clock gating
    • Multi-VTH optimization and placement
    • Multi-VDD, MTCMOS
  • Clock tree placement and balancing
  • DFT implementation including 3rd-party IP integration
  • ATPG with more complete fault models
  • Timing closure with post-route SI optimization analysis and repair
  • Configuration tech file modifications for routing
  • Scan compression
  • Multi-corner, multi-mode (MCMM) optimization and analysis
  • Rail analysis to address IR drop and electromigration
  • Chip finishing, including metal fill, spare-cell and Dcap insertion
  • LVS and DRC on sub-blocks and top-level
  • Recommend and implement flow and methodology enhancements, including SI-aware, power-area and yield-aware place and route
  • Advanced Node flow updates for faster design closure like DPT and FINFET for sub-20nm nodes
  • Optimizing and hardening High Performance Cores from leading vendors like ARM, Imagination etc. for customer specific configurations and PPA targets

Customer Case Study
To mitigate their tapeout risks and achieve critical schedule milestones, a global leader in wireless chipsets turned to Synopsys for assistance with a complex multi-channel design incorporating 40 clock domains. Synopsys consultants joined the customer's design team to ensure cell utilization was optimized and the highly complex clocking architecture was correctly implemented. Synopsys' onsite support in the final weeks of tapeout focused on synthesis, clocktree balancing and latency control to ensure timing closure was achieved and performance targets were met. Timing closure was achieved across both synchronous and asynchronous paths. The CTS methodology and scripts developed in the course of the project were adopted and applied to several subsequent designs.

Tapeout Assist Fig2

Figure 2: Clock buffers and clock gates were inserted and resized to meet skew
and latency goals as well as reduce power. This enabled the design team to
achieve timing closure across all synchronous and asynchronous

Synopsys assists customers in achieving more than a hundred successful tapeouts every year. These designs span a broad spectrum of application areas, chip sizes and complexity, and process nodes. This extensive resume enables our consultants to draw upon valuable experience of the issues and solutions associated with getting a chip to tapeout, helping you to avoid costly delays.

Tapeout Assist Fig3

Table 1: Sample of recent Synopsys-assisted customer tapeouts

For more information about Synopsys' complete portfolio of consulting and design services, visit www.synopsys.com/sps or contact your local Synopsys sales representative.

For more information about Galaxy™ tools and tool flows, visit http://www.synopsys.com/Tools/Pages/default.aspx.



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