- Complement your design team with experts in SI, power, DFT, DFM, and verification
- Adopt best-practices and new methodologies
- Dedicated project assistance through tapeout
Leverage Tapeout-proven Flows And Project Experience To Get Your Chip Done
Getting your chips into volume production on a fast, predictable schedule becomes more and more difficult with each new process node. At advanced geometries, the risk of a protracted design cycle – and its associated cost burden – becomes a real threat to the health of your business or product development program.
The extraordinary levels of integration afforded by very deep sub-micron (VDSM) processes amplify the challenges in physical design. Closing timing in a predictable manner at both the block and chip levels requires a thorough understanding of VDSM effects. While timing, signal integrity, testability, and power issues are first order considerations, their interdependencies further complicate design closure. Leveraging deep expertise in the tools and specializing in RTL- to-GDSII design services, Synopsys consultants help you achieve an optimized block- or chip-level implementation in the fastest possible timeframe. Design teams can also utilize Synopsys’ web-based design infrastructure; this collaborative “virtual” environment enables the project team to leverage people and compute resources anywhere in the world, any time of the day. Additionally, access to an extensive server farm with scalable hardware and software resources accelerates productivity during critical design phases.
Through hundreds of projects and more than 15 years of working with our customers on their most challenging chip designs, Synopsys Professional Services has established a leading-edge design competency, with consultants skilled in the latest EDA technology and design practices. Synopsys consultants understand the issues that most commonly impede progress in the physical design phase – from constraints management to power distribution and clocking to DRC/LVS integration issues – and possess the expertise and experience to develop practical action plans with your design team. And because the path to a successful tapeout is often lined with challenges that only become critical late in the design cycle when they are highly visible, our consultants can provide dedicated physical design assistance through tapeout. The Synopsys on-site staff is backed by a worldwide network of consulting, CAE and R&D resources. While the primary objective is completing your current design project on spec and on schedule, our services often lead to flow and methodology enhancements as well as knowledge transfer that improve your team’s readiness for their next design program.
- Synopsys’ Physical Design Assistance services include:
- Hierarchical budgeting and design planning
- SI-aware place & route
- Full-chip timing/SI closure, static timing analysis and sign-off
- Qualifying libraries, existing RTL and design constraints
- Generating and optimizing clock trees
- Power planning and optimization
- Scan compression
- Multi-corner, multi-mode (MCMM) optimization and analysis
- Rail analysis to address IR drop and electromigration
- Full-chip extraction and in-design physical verification
- Targeted tapeout assistance
- Constraints management at block and chip level
- Clock tree placement and balancing
- DFT implementation including 3rdparty IP integration
- ATPG with more complete fault models
- Timing closure with post-route SI optimization analysis and repair
- Configuration tech file modifications for routing
- Chip finishing, including metal fill, spare-cell and Dcap insertion
- LVS and DRC on sub-blocks and top-level
- Adopting demonstrated methods and baseline scripts for follow-on project use
- Netlist, placed-gates, or GDSII manufacturing handoffs as well as concept-to-parts services through unique alliance with Honeywell for next-generation rad-hard ASICs
To get more information on how we can customize our services to help you meet your design goals, please contact us or call your local Synopsys sales representative.