Integrating both analog and digital blocks into a single chip poses a variety of verification challenges, including ensuring functional correctness from the block to the system-level and validating the analog/ digital interface. Designers must address complex simulation configurations for multiple design views, and make difficult verification trade-offs for speed, accuracy and capacity. Often design teams are challenged with developing an optimum co-simulation environment because few designers have expertise that spans both the digital and analog realms.
Synopsys' Co-Simulation (“co-sim”) Flow Assistance service helps design teams find chip-level bugs by establishing a comprehensive flow for verifying across digital and analog domains. By leveraging the advanced product features and methodologies built into Synopsys' VCS®, NanoSim® and HSIM® simulators, Synopsys consultants assist in developing and deploying a robust co-simulation flow which meets system-level performance and accuracy requirements. The co-sim flow integrates the analog and digital netlists at various levels of abstraction. Selected test cases are simulated and the results are analyzed to ensure correct configuration.
Synopsys consultants also help ensure that correct multi-level views are configured and connectivity across the transistor and RTL boundaries are simulated correctly. The comprehensive flow can be implemented in either a topdown or bottom-up methodology.
Synopsys' highly-trained consultants combine an understanding of analog/ mixed-signal and digital design issues with extensive tool knowledge to deliver expert on-site services. The knowledge transfer of methodologies and best practices to your team will enable the optimized flow to be re-used across projects.
Figure 1. Synopsys Discovery Analog/Mixed-Signal (AMS) Verification Flow.
- On-site consultants bridge the knowledge gap between analog and digital teams
- Develop a reusable and scalable AMS co-simulation flow that performs analog timing and power checks at chip level, A-to-D connectivity checks
- Support for multiple languages (e.g., Verilog, VHDL, SystemVerilog) and levels of abstraction (behavioral, RTL, transistor)
Figure 2. Advanced tool features and methodologies supported by Synopsys' simulators address common co-simulation issues such as dissimilar timing skews at block and chip levels, unconnected nets at the chip level, passing supply nets from the analog to digital domain, unresolved cross module references (XMR), and timescale precision. The optimized flow helps meet speed and accuracy requirements as well as the need to handle multiple views by providing a unified partition file.
Customer Case Study
An industry leading ASIC design company working on a multi-GHz design had difficulty in fully verifying the chip-level functionality due to long transistor netlist simulation times. The design had multiple data channels with large amounts of memory required to simulate each channel. This made it extremely difficult to conduct concurrent transistor-level simulations for the entire ASIC, resulting in co-simulation as the critical bottleneck in the tape-out schedule.
Synopsys consultants analyzed the customer's prior tapeouts and recommended a single partition file to manage multiple design views. The use of different abstractions for multiple channels helped reduce the memory requirements and sped up the simulation significantly. Synopsys AMS consultants worked with the customer's design team to deploy an optimized, unified co-simulation flow that could be adopted early in the design cycle. This design assistance, coupled with sharing of best practices, helped eliminate verification issues that would have delayed the tapeout schedule.
For more information about Synopsys' complete portfolio of consulting and design services, visit: www.synopsys.com/Services
For more information about Discovery tools and flows, visit: http://www.synopsys.com/Solutions/EndSolutions/DiscoveryVerification/Pages/default.aspx