DesignWare DDR Memory Interface IP Hardening Services 


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  • Low risk, single source for DDR controllers, PHYs and services
  • DDR experts dedicated to your project success
  • Experience with multiple DDR configurations and technologies
  • Services for PHY hardening or controller and PHY hardening

With over 700 DesignWare® DDR Memory Interface IP design wins, Synopsys is best positioned to help you with your DDR design needs. Our experts can provide RTL-to-GDSII services to harden a DesignWare DDR IP core and assist with integration into the System-on-Chip (SoC). Figure 1 illustrates a DesignWare DDR and universal controller implementation. Every design is unique and with our complete DDR IP architecture-to-GDSII experience, we can help you achieve your design goals.

DDR Hardening Services

Figure 1: Synopsys DesignWare DDR IP core implementation

DDR Hardening Services
Synopsys DDR experts will take your unique inputs including DesignWare DDR PHY IP configuration, RTL, IO pad order, block-level and SoC constraints (i.e. target frequency, data/address widths, DDR shape requirements, signal|power|ground ratio and signoff corners) and do the physical design to harden your DDR PHY IP according to your specific SoC requirements. Hardening is split into preliminary and final implementation phases to provide an intermediate review step that provides an opportunity to make appropriate changes to the design constraints before final implementation.

DDR Hardening Services

Figure 2: Synopsys RTL-to-GDSII DDR IP hardening services and deliverables

Upon completion of the services, as shown in Figure 2, Synopsys will deliver to the customer the hardened DDR.

Deliverables include:
  • Milkyway CEL models and FRAM views
  • Abstract Models
  • All corner chip parasitics (SPEFs)
  • Signoff reports

Also up-to five days of on-site physical design assistance to help with integration of the DDR PHY into the SoC is typically included. Optional DDR PHY and controller hardening services are available for customers requiring assistance for both a PHY and controller.

Other Related Services
In addition to DesignWare DDR memory interface IP hardening services, Synopsys provides a wide range of other services to assist with your design needs including:
  • DDR PHY Signal Integrity Report service
  • Tape-out Assistance
  • Core Optimization
  • Tool and Methodology Consulting
  • Design Flow Deployment
  • IP Integration and SoC Verification
  • FPGA-Based Prototyping

About Professional Services
Synopsys Professional Services assists customers in achieving more than a hundred successful tape-outs every year. These designs span a broad spectrum of application areas, chip sizes and complexity, and process nodes. This extensive resume enables our consultants to draw upon valuable experience of the issues and solutions associated with getting a chip to tape-out, helping you to avoid costly delays.

For more information on Synopsys’ complete portfolio of consulting and design services, visit or contact your Synopsys sales representative at +1.650.584.5000.

About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols, analog IP, embedded memories, logic libraries, processor cores and subsystems. To support software development and hardwaresoftware integration of the IP, Synopsys offers drivers, transaction-level models, and prototypes for many of its IP products. Synopsys’ HAPS® FPGA-Based Prototyping Solution enables validation of the IP and the SoC in the system context. Synopsys’ Virtualizer™ virtual prototyping tool set allows developers to start the development of software for the IP or the entire SoC significantly earlier than traditional methods. With a robust IP development methodology, extensive investment in quality, IP prototyping, software development and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk.

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