- Experienced engineers optimize leading-edge core implementations for performance, power consumption and area
- Jump start your implementation team with best-practices and new methodologies
Compete effectively with a processor core that’s tailored for your application
Reminiscent of the “MHz wars” in the PC industry, performance often headlines product announcements. But, designers rarely have the luxury of pursuing speed at all costs. Consumer and mobile device users care about battery life and product cost. Even developers of teraflop-class servers must consider how energy consumption impacts power supplies, reliability and cooling costs. Processor cores (i.e., CPUs and GPUs) are some of the most critical IP blocks in most SoC designs.
The processor core’s achievable performance, power and area (PPA) is impacted by several interacting factors. The number of cores, the size and organization of cache memories, the underlying silicon process and the expected ranges of operating conditions and manufacturing variations are among the more obvious parameters that need to be considered for each specific design. Other factors, like features of standard-cell libraries and embedded memories, test and debug logic, power control circuits, clock noise and on-chip variation can also have a significant impact on achievable PPA results. Understanding the tradeoffs in performance, power and area – as well as development cost and schedule – is important for project success making core optimization a complex process.
Figure 1: Optimized results require specialized expertise
As Figure 1 illustrates, for complex designs, conventional flows and design techniques only get you part way to the best possible PPA. Maximum PPA results are achieved with optimized flows, deep tool expertise and design-specific implementation experience.
Synopsys Professional Services has extensive experience optimizing CPU and GPU cores on hundreds of projects at leading process nodes. Leveraging Synopsys’ industry-leading Galaxy™ Implementation Platform and Lynx Design System, design consultants deliver core optimization assistance starting from design planning – where accurate alignment of the cache memories and positioning to minimize critical paths ensures the fastest possible implementation – through place and route and signoff. Synopsys’ experienced core optimization consultants use proven best practices to ensure optimal settings for synthesis (critical range, path groups; advanced techniques with SPG), placement (bounds, soft & hard regions), clock tree synthesis (skew optimization and minimization, advanced techniques with clock mesh and multi-source) and routing (layer assignment for performance and SI prevention).
Synopsys’ assistance with final manual tuning and optimizations helps ensure that customers achieve a design uniquely optimized for their PPA goals.
Table 2 describes optimization techniques and best practices applied by Synopsys consultants to achieve optimal results.
Table 2: Experienced Synopsys experts apply best practices to optimize PPA and yield
- Synopsys’ Core Optimization Services include:
- Configure core RTL, cache partitioning
- Configure flow: tech files, libraries, memories
- Update floorplan: relative memory placements
- Initial performance analysis
- Early flow optimizations
- Establish QoR limits: performance, power, area
- Analyze multi-Vt and multi-channel cell usage
- Iteratively address bottlenecks and critical paths
- Finalize IC Compiler optimizations
Find more information about factors impacting the optimization of processor cores, see the white paper: Reality Check: A Guide to Understanding Optimized Processor Cores
For more information about Synopsys’ complete portfolio of consulting and design services, visit www.synopsys.com/sps or contact your local Synopsys sales representative.