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Staying competitive in today's digital consumer market increasingly requires building complex systems with a small and well defined time-to-market. The integration of third-party, ready-touse IPs is therefore becoming wider as a way reduce design and verification efforts. Giovanni Strano, Carlo Pistritto, STMicroelectronics
Salvatore Tiralongo, Synopsys Professional Services
Euro DesignCon 2004
This paper describes the state-of-the-art in low power design optimization methodologies and EDA solutions for active power reduction. We shall explain the principles of dynamic power reduction design optimization methods including smart clock gating, glitch reduction and dynamic voltage scaling. We shall discuss the related challenges for EDA in implementation of these methods, such as optimal clock gating insertion and placement, voltage domain aware automatic power planning, level shifter insertion and placement, power island award full chip design synthesis and physical optimization, and multi-voltage clock tree generation and routing. James Shiffer, Artisan Components, Inc.
Jason Binney and Kaijian Shi, Synopsys Professional Services
In this paper, we shall describe the state-of-art in design optimization methodologies and EDA solutions for leakage power reduction in sub-90nm technology. We shall describe principles of leakage power reduction design optimization methods including threshold voltage scaling, dual-Vth design optimization, state assignments and pin-reordering. We shall also describe power-gating methods that shut off power supplies to idle function blocks in standby mode and design optimization methodologies of power-gating designs. Kaijian Shi, Synopsys, Inc.
Jason Binney, Synopsys, Inc.
As today’s design complexity grows, verification has become one of the biggest challenges. Many verification technologies, such as constrained random verification, assertions and functional coverage, have been introduced. However, it is the verification methodology that builds a verification environment that takes full advantage of these technologies to solve complex verification challenges. This paper exhibits the reference verification methodology (RVM) for Vera and how it is applied to a networking design case study. Cristian Samoila, CIENA Inc
Jason C. Chen, Synopsys Professional Services
This paper presents a methodology for a SoC-level response checker that utilizes a queuing system in order to track data through the device. The response checker architecture is an end-to-end data checker that uses the Freescale base classes and Vera® Smart Queues to create reusable and easy-to-follow verification code. The response checker was designed as part of a Synopsys Professional Services engagement with a Freescale design team. This paper also conveys experiences and lessons learned using a real chip design flow. Fraya H. Cohen, Synopsys Professional Services
Chi Duong, Freescale Semiconductor, Inc.
ESNUG 2004Joachim Geishauser, Motorola
Anthony Ezell, Synopsys Professional Services
SNUG Europe 2004
Why should we use PC-Astro flow instead of the introduced DCPC-Astro flow: to get better QoR for power, timing, IR drop and related effects. In DCPC-Astro design flow the RTL code is first read into Design Compiler to synthesize the initial netlist for floorplanning. The DC synthesis is done with statistical wireload models from design library. DC Synthesis approximates wire lengths, but those seldom correspond close enough with the real wire lengths of placed and routed design. Juha Liias, Synopsys Professional Services
We just completed an R&D project that contained multiple AMBA IP blocks which all had to be integrated and verified in our environment. We had multiple IP blocks that had AHB interfaces, and some with APB interfaces. Some IP blocks had no AMBA interface, and we had to design our own AMBA interface. We also integrated a PowerPC CPU using a proprietary PLB2AHB bridge. Chris LeBlanc, Jeff Alderson, Synopsys Professional Services
On a recent project, a team from Synopsys Professional Services designed a large system using a Xilinx Virtex II Pro FPGA. Due to availability of Xilinx parts, we started with XC2VP50, and later moved up to XC2VP70 devices (in the same package). We used the hard Power PC macro, and 4 of the differential Gigabit Rocket I/O Transceivers. We were severely area limited in the 50 device, and had very aggressive timing goals (a large part of the FPGA ran at 125 MHz, with a 64 bit datapath). Jeff Alderson, Synopsys Professional Services
SoC Conference 2004, Sweden
Increased complexity of System-on-Chip (SoC) designs caused by trend towards higher integration and reduced system cost is demanding higher design productivity to manage SoC development cost, time and effort. Semiconductor intellectual property (IP) has become the prevalent form of accelerating the design cycle. However, there are other reasons for IP use such as ensuring interoperability with other components and avoiding design errors with pre-verified blocks. While design reuse is already a common design practice, Gartner Dataquest predicts that by 2005, 80% of SoC consists of reused blocks. Jyrki Hyrsylä, Juha Peltoniemi and Pekka Leinonen, Synopsys Professional Services
A new design optimization method has been developed to combine strength of the subchip based hierarchical optimization methods for efficiency and the flat design based optimization method for quality. A virtual hierarchy concept has been developed for the method to enable efficient logic and physical combined design optimization on a distributed computing environment. As the result, it becomes achievable to optimize a multi-million gate design as efficiently as that of the hierarchical design optimization with a quality of result as good as that of the flat design optimization. Thi Nguyen, Kaijian Shi, Synopsys, Inc.
Confidence in the quality of the used IP is critical in any IC development but especially critical if the IP is aimed at external distribution. This confidence is achieved by measuring such things as code coverage (line, toggle and conditional) and state transitions and having these at 100%. Code coverage is one of the important measures to the completeness and comprehensiveness of the test bench. The coverage challenge is even greater with configurable IP designs. Changing some of the IP configuration parameters can result with a new design and complicates code coverage by having to analyze over many different base designs. Hani Saleh, Peter Gillen, Synopsys Inc.
SNUG San Jose 2004
In the past, pad ring connectivity on previous projects was verified using hundreds of directed tests. There are more than ten thousand signals defining what gets connected to 300 different pins on the chip. Small changes in the design required rewriting and retesting many of the patterns. It was laborious and time consuming, yet bugs still escaped. If these bugs are found post-silicon, it will be an expensive fix. Motorola was looking for a solution to increase its confidence of producing first silicon with zero defects. OVA technology offered the way out. Laucresha Salmon, Motorola, Inc.
Hemendra Talesara, Synopsys, Inc.