Early availability coupled with high performance makes rapid prototyping a widely adopted ASIC verification methodology. Synopsys’ Confirma™ platform is a tightlyintegrated combination of software tools and off-the-shelf FPGA-based hardware that enables rapid and scalable prototype implementations. A Confirma-based flow accelerates the functional verification of FPGAs and ASICs, providing enhanced visibility into the hardware to help uncover hard-to-find bugs. Pre-silicon availability of the system prototype translates into an early start for software development as well.
Prototyping Assistance services from Synopsys help you deploy the Confirma flow to efficiently map your ASIC-targeted RTL to Synopsys’ High-performance ASIC Prototyping System (HAPS™) hardware. Synopsys consultants work collaboratively with your design team, sharing expertise with the Confirma tools, helping deploy optimized methodologies and flows, and assisting with the prototype implementation. The focus is creating a robust, reusable prototyping flow while minimizing the need for RTL changes. On-site assistance facilitates knowledge and best practice sharing to not only accelerate deployment for your current project, but positively impact your future programs as well.
- Develop prototyping methodology and deploy flow
- Map ASIC-targeted RTL to HAPS hardware
- Optimize setup for RTL debug and software development
Figure 1: Confirma’s integrated hardware/software flow
Synopsys’ Prototyping Assistance offers dedicated specialists that can help you:
- Map your design into the HAPS hardware, including
- Analysis of your prototyping goals
- Defining an optimal prototyping setup
- Creating a prototyping project plan as an integral element of the system-level verification plan
- Analyze key aspects of your design for adaptation, such as
- Implementing gated clocks in FPGAs
- Mapping ASIC memories to FPGAs
- Partitioning and pin-multiplexing to map large designs
- Implementing appropriate debug strategies and flows
- Analyzing 3rd-party IP requirements for FPGA implementation
- Reusing feasible parts of Design Compiler scripts
- Configuring hardware clocking resources
- Create a streamlined FPGA i mplementation process
- RTL instrumentation to improve visibility during hardware debug
- Logic partitioning to map large SoC designs into multiple target FPGAs
- Synthesis of single or multiple FPGAs in parallel
- Place and route using Xilinx ISE software (customers must obtain directly from Xilinx)
- Configure the following aspects of the modular HAPS platform
- Clock configuration
- Daughter card configuration– memory, standard interfaces etc.
- Remote connectivity to allow network access to HAPS hardware
- Run built-in self test
- Setup for system-level debug using appropriate lab equipment
For more information about Synopsys products, support services or training, visit us on the web at: www.synopsys.com, contact your local sales representative or call 650.584.5000.
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