- Download Datasheet
- Augment your front-end design team with physical design experts to incorporate physical information early in the design cycle
- Produce physically-aware netlists that reduce back-end iterations, improve ASIC handoff
Early Optimization For Physical Effects Improves Netlist Handoff
For modern chip designs, a comprehensive synthesis plan must balance the competing requirements of smaller geometries, greater complexity and optimal performance, along with the corresponding physical effects on timing and congestion.
A traditional ASIC or netlist handoff is becoming inefficient, as multiple, expensive iterations between customer and ASIC vendor, or between front-end and backend design teams within the same company, compromise both productivity and predictability. It is increasingly difficult for design teams to produce a netlist that meets the sign-off criteria from the ASIC vendor or physical design team, which now must include routability and congestion thresholds. With more constraints to optimize, such as multiple analysis modes and operating corners, physical data must be incorporated earlier in the design flow to improve design predictability.
A “physically-aware” flow, unlike a traditional ASIC flow, incorporates physical data throughout the design process. Synopsys consultants have extensive experience throughout the entire design flow, on some of the industry’s most advanced chips, from specification to tapeout. We can augment your front-end design team with physical design methods and expertise to help eliminate expensive iterations with back-end teams. By utilizing physical implementation tools and analysis techniques earlier in the flow (e.g., during the physical synthesis step), the resulting physicallyaware netlists can incorporate design intent, floorplan data, utilization and congestion optimization for a more efficient hand-off to the physical implementation team.
Figure 1: In a traditional ASIC flow, numerous iterations between the front-end team and the back-end team are often necessary to converge on a netlist which can be implemented and taped out. With more complex designs at leading technology nodes, the back and forth cycle between design teams to achieve design convergence gets significantly longer and unpredictable.
Figure 2: In the new physically-aware flow, physical information and guidelines are used by the front-end design team to create a netlist which takes into account the back-end requirements and restrictions. The resulting physically-aware netlist is more easily implemented, with improved quality of results and better schedule predictability.
- Synopsys’ Predictable Silicon Sign-Off services include assistance with:
- Incorporating physical information early in the design cycle
- New and complex library characteristics
- Multi-voltage thresholds and multiple voltage domains
- Multiple PVT corners, operating mode constraints, and clocks
- Floorplan constraints
- New physical requirements such as minimum double-via requirements
- New test and verification strategies such as hierarchical scan
- Producing physically-aware netlists which take into account
- Incorporated low power techniques, special cells
- Cell utilization
- Special ASIC vendor physical requirements
To get more information on how we can customize our services to help you meet your design goals, please contact us or call your local Synopsys sales representative.