Low Power Optimization and Verification Datasheet 

 
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At-A-Glance
  • Understand and apply optimal set of low power techniques to achieve design goals
  • Take advantage of voltage-aware functional verification technologies
  • Deploy UPF-based flows to achieve rapid power closure

Implement Low Power Techniques To Optimize Your Chip’s Power Consumption
Increases in the size and complexity of today’s SoC designs have intensified the challenges of low power optimization and verification.

With expertise in low power tools and techniques, Synopsys consultants can help you manage your chip’s dynamic and leakage power consumption. We will help you understand the inherent tradeoffs in using power-related technologies such as voltage islands, power and clock gating, multi-voltage design, dynamic voltage scaling, multiple threshold voltages, and MTCMOS while helping you deploy the new standard for describing low power design intent, IEEE 1801-2009 – Unified Power Format (UPF). With your project requirements in mind, our consultants can then assist you in deploying the latest low-power techniques throughout the entire design flow, from synthesis, to functional verification and clock tree synthesis, through implementation and post-route optimization.

With the number and complexity of low-power design techniques escalating, verification of designs containing these techniques has become more challenging. As a low power design moves from one operating mode to another, comprehensive power-aware verification in all of the power states is required. Synopsys consultants can help you deploy new technologies that deliver the required accuracy and verification coverage for power-managed designs, including multi-voltage simulation and multi-voltage static checks.

Synopsys’ Low Power Optimization and Verification services include assistance with:
  • Low power optimization and implementation
    • Assess current low-power techniques and methodologies including design intent (e.g., varying performance requirements), power constraints and scripts review
    • Recommend and deploy new low-power methodologies including appropriate use of advanced low-power standards and techniques:
      • IEEE 1801-2009 based on Accellera’s Unified Power Format (UPF)
      • Multi-voltage design and integration
      • Power gating with MTCMOS
      • Multi-Vth
      • Clock-gating
      • Dynamic Voltage-Frequency Scaling (DVFS)
      • Chip rail analysis and sign-off
    • Develop new scripts and integrate them for project use
    • Develop low power test plan
  • Low power verification
    • Customize low power verification test plan to guide simulation and coverage
    • Verify low power constructs such as isolation, power switches, and register retention
    • Verify protection cells added by synthesis, such as isolation cells, level-shifters, and retention registers
    • Verify implementation of power network added during place-androute
    • Ensure UPF description is matched


Eclypse Low Power Solution

To get more information on how we can customize our services to help you meet your design goals, please contact us or call your local Synopsys sales representative.



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