Traditionally, analog/mixed signal (AMS) designs have had lower verification coverage due to a lack of diagnostic capabilities and simulator features necessary for capturing circuit design errors. At times, incomplete vector sets may also contribute to this issue. As a consequence, simulation effort is wasted on incorrect netlists and, more importantly, costly silicon re-spins can be incurred due to design errors that go undetected until post-tapeout testing. Synopsys HSIMplus™ CircuitCheck™ services can help you significantly improve verification coverage by identifying potential trouble spots –such as connectivity issues, excessive current, glitches, and un-initialized latches – prior to and during simulation.
Synopsys' highly-trained consultants combine an understanding of AMS design issues with extensive tool knowledge to deliver expert on-site services. They will assist you in deploying a flow that performs:
- Low-power design and static leakage checks
- Signal integrity and timing checks
- Geometrical and electrical error checks (parametrics)
- Design and electrical rule checks
- Digital logic/memory diagnostics
Figure 1. HSIMplus CircuitCheck solution increases verification coverage and discovers potential trouble spots early in the design cycle.
- Assess circuit checking needs to deploy reusable, optimized AMS flow
- Address design specific challenges using customizable rules and command files
- Analyze CircuitCheck reports for violations
- Provide on-site training from experienced consultants to facilitate knowledge transfer and improve productivity
Figure 2. A comprehensive CircuitCheck solution includes creation of CCK rules, static and dynamic checks, and reporting analysis.
The verification flow shown in Figure 2 employs the HSIMplus™ CircuitCheck simulator, which runs static and/or dynamic checks that can be modular or hierarchical, to identify circuit design rule violations and provide detailed output reports in an automated fashion. This approach is significantly less time consuming and less error prone than manual checking, enabling more comprehensive coverage before tape-out.
Synopsys consultants can assist with implementing a flow that runs your transistor level netlist against design specific rules and ensures that errors are caught before they impact your project schedule. Consultants will also train on the best-practices to ensure the optimized flow can be re-used across projects.
Customer Case Study
A leading programmable IC device company needed to dramatically improve circuit design verification quality and reduce simulation time for a multi-voltage mixed-signal design. Prior to upgrading their verification flow, tedious and error-prone manual checking was required to identify delays caused by parasitic effects. Synopsys consultants helped the customer implement dynamic checks to capture these parasitic delays. Simulations that previously took weeks could now be accomplished in a day.
In addition to time-consuming manual checks, the company's traditional simulation approaches lacked the capability and practicality to run VDD node checks between the digital and analog blocks. Synopsys consultants helped develop command files with rule-based checks for the customer's HSIMplus™ CircuitCheck environment, which identified incorrect VDD node assignments between the digital and analog partitions (reference Figure 3).
Figure 3. Multi-voltage design with monitoring checks.
For more information about Synopsys' complete portfolio of consulting and design services, visit: www.synopsys.com/Services
For more information about Discovery tools and tool flows, visit: www.synopsys.com/Solutions/EndSolutions/DiscoveryVerification