HAPS Jumpstart ds

At-a-Glance

Overview
Synopsys’ Confirma™ Rapid Prototyping Platform provides a tightly integrated, comprehensive, rapid prototyping flow that accelerates the functional verification of FPGAs and ASICs. Confirma, and the High-Performance ASIC Prototyping System (HAPS™) hardware and associated software, is ideal for IP and SoC design and verification teams who take advantage of FPGA-based prototyping to find “cornercase” hardware bugs or to start software development and integration in advance of ASIC availability.

The HAPS Jumpstart training helps designers understand and apply an atspeed SoC prototyping methodology using Synopsys’ Confirma Platform. The Jumpstart training delivers five days of on-site services to assist you in setting up a comprehensive rapid prototyping flow customized for your design environment. The collaborative, hands-on deployment model accelerates the integration of prototyping into your overall verification plan while advancing your design team’s knowledge of Confirma-based methodologies and implementation. Synopsys will adapt the HAPS Jumpstart to your team’s experience level with FPGA prototyping. Typical Jumpstart engagements include:

Prototyping Flow Training
Classroom-style instruction provides new HAPS users with hands-on training that covers key tool features and methodologies using a sample design. The duration and topics for the training vary based on users’ expertise and project requirements. A typical multi-day agenda covers the following:

RTL design for FPGA implementation
Logic synthesis for FPGA
Partitioning large designs into multiple FPGAs
Detailed analysis of hardware results to facilitate debug
Xilinx place-and-route software overview

Planning and Setup
Once users are familiar with the HAPS flow, a review of your verification plan and prototyping goals is conducted. This review enables Synopsys consultants to assist you in creating a prototyping project plan that specifies the appropriate setup and configuration required. Portions of your actual RTL code can be used to setup and illustrate the key aspects of the prototyping flow, including:

Handling gated clocks
Mapping ASIC memories to FPGAs
Partitioning and pin-multiplexing to map large designs
Strategies and options to facilitate design debug
3rd-party IP considerations for FPGA implementation
Evaluating optimal prototyping performance vs. effort
Analyzing Design Compiler® scripts to determine constraints
Configuring hardware clocking resources

Figure 1: Integrated rapid prototyping flow using the Confirma platform with required
and optional Jumpstart components

HAPS Hardware Configuration
Once the flow is set up and the RTL design is ready for FPGA mapping, HAPS is configured. Using the HAPS hardware available at your site, your engineers will get hands-on experience configuring HAPS to address:

Specific power supply connections and built-in self-test
Component connectivity and clock configuration setup
Supervisor control circuit configuration
JTAG interface setup between the workstation and HAPS
Hardware remote control configuration via LAN
Debug and visibility instrumentation using MICTOR cards, a logic analyzer and Synopsys’ Identify® RTL debugger

Additional Training (Optional)
Depending on participants’ familiarity with the Confirma verification platform, Synopsys consultants can augment the Jumpstart training in the following areas:

Certify® Pin Multiplexing (CPM) to time-share I/O pins
Synplify® Premier features for in-system debug and faster timing closure
In-depth HAPS hardware configuration
HAPS custom daughter card considerations

Jumpstart Prerequisites

For more information about Synopsys products, support services or training, visit us on the web at: www.synopsys.com, contact your local sales representative or call 650.584.5000.

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