FPGA-Based Prototyping Jumpstart 

Specialized Training and Setup Support for FPGA-Based Prototyping Adopters 

The Synopsys FPGA-based prototyping solution provides a tightly integrated, comprehensive prototyping flow that accelerates the functional verification of FPGAs and ASICs. The Synopsys FPGA-based prototyping solution is ideal for SoC design and verification teams who take advantage of FPGA-based prototyping to find “corner-case” hardware bugs or to start software development and integration in advance of ASIC availability.

The Jumpstart training helps designers understand and apply Synopsys FPGA-based prototyping hardware and software solution to dramatically accelerate ASIC, ASSP and SoC designs. The Jumpstart delivers five days of on-site services to assist you in setting up a comprehensive FPGA-based prototyping flow customized for your design environment. The collaborative, hands-on deployment model accelerates the integration of prototyping into your overall verification plan while advancing your design team’s knowledge of FPGA-based prototyping methodologies and implementation.

Synopsys will adapt the Jumpstart training to your team’s experience level with FPGA-based prototyping. Typical Jumpstart engagements include:

Prototyping Flow Training
Classroom-style instruction provides new Synopsys FPGA-based prototyping users with training covering key tool features and methodologies. A sample design is used for the training. Though the duration and topics for the training vary to align with users’ expertise and project requirements, the typical multi-day agenda covers the following:

  • RTL design for FPGA implementation
  • Logic synthesis for FPGA
  • Partitioning large designs into multiple FPGAs
  • Increasing visibility in the hardware to facilitate debug
  • Xilinx place and route software overview

Planning and Setup
Once users are familiar with the Synopsys flow, a review of your verification plan and prototyping goals is conducted. This review enables Synopsys consultants to assist you in creating a prototyping project plan that specifies the appropriate setup and configuration required. Portions of your actual RTL code can be used to setup and illustrate the key aspects of the prototyping flow, including:

  • On-site FPGA-based prototyping flow training
  • Prototyping methodology development
  • Working examples of RTL to FPGA mapping based on your design style
  • HAPS hardware setup and configuration
  • Handling gated clocks
  • Mapping ASIC memories to FPGAs
  • Partitioning and pin-multiplexing to map large designs
  • Strategies and options to facilitate design debug
  • 3rd-party IP considerations for FPGA implementation
  • Evaluating optimal prototyping performance vs. effort
  • Analyzing Design Compiler scripts to determine constraints
  • Configuring hardware clocking resources

Upon the completion of this phase, working examples of the flow mapping the ASIC-targeted design into FPGAs should be in place.

Integrated rapid prototyping flow using the Confirma platform
Figure 1: Integrated FPGA-based prototyping flow

Hardware Configuration
Once the flow is setup and the RTL design is ready for FPGA mapping, Synopsys’ High-performance ASIC Prototyping System (HAPS®) is configured. Using the HAPS hardware available at your site, your engineers will get hands-on experience configuring HAPS to address:

  • Specific power supply connections and built-in self-test
  • Component connectivity and clock configuration setup
  • Supervisor control circuit configuration
  • JTAG interface setup between the workstation and HAPS
  • Hardware remote control configuration via LAN
  • Debug and visibility instrumentation using MICTOR cards, a logic analyzer and Synopsys’ Identify RTL debugger

Additional Training (Optional)
Depending on participants’ familiarity with our FPGA-based prototyping tools, Synopsys consultants can augment the Jumpstart training in the following areas:

  • Certify® Pin Multiplexing (CPM) to time-share I/O pins
  • Synplify® Premier features for in-system debug and faster timing closure
  • In-depth HAPS hardware configuration
  • HAPS custom daughter card considerations

Jumpstart Training Prerequisites
  • Certify software license installed
  • Xilinx ISE software license installed
  • Xilinx JTAG download cable available

The following are recommended in order to ensure the most efficient Jumpstart training delivery schedule:

  • Required HAPS components available on-site
  • Certify-compiled RTL code
  • Lab area for system setup and HAPS hardware

For more information about Synopsys products, support services or training, visit us on the web at: www.synopsys.com, contact your local sales representative or call 650.584.5000.

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