CHIPit Jumpstart ds

At-a-Glance

Overview
Synopsys’ Confirma™ Rapid Prototyping Platform provides a tightly integrated, comprehensive rapid prototyping flow that accelerates the functional verification of FPGAs and ASICs. Confirma, and the CHIPit® line of ASIC prototyping systems and associated software, is ideal for IP and SoC design and verification teams who take advantage of FPGA-based prototyping to find “corner-case” hardware bugs or to start software development in advance of ASIC availability.

The CHIPit Jumpstart training helps designers understand and apply a selected SoC prototyping methodology using Synopsys’ Confirma Platform. The Jumpstart training delivers five days of on-site services to assist you in setting up a comprehensive rapid prototyping flow customized for your design environment. As part of the training, a review of your verification plan and prototyping goals is conducted. This review and discussion enables Synopsys consultants to assist you in creating a prototyping project plan that specifies the appropriate setup and configuration required. The collaborative, hands-on deployment model accelerates the integration of prototyping into your overall verification plan while advancing your design team’s knowledge of Confirma-based methodologies and implementation. Synopsys will adapt the CHIPit Jumpstart to your team’s experience level with FPGA prototyping. Typical Jumpstart engagements include:

Prototyping Flow Training
Classroom-style instruction provides new CHIPit users with hands-on training that covers key tool features and methodologies using a sample design. The duration and topics for the training vary based on users’ expertise and the project requirements. A typical multi-day agenda covers the following:

RTL design for FPGA implementation
Logic synthesis for FPGA
Partitioning large designs into multiple FPGAs
Understanding and usage of debug capabilities

Figure 1: Integrated rapid prototyping flow using the Confirma platform with required
and optional Jumpstart components

Methodology Selection Planning and Setup
Once users are familiar with the CHIPit flow, a sample design will be used to setup and illustrate the key aspects of the prototyping flow, including:

Handling gated clocks
Mapping ASIC memories to FPGAs
Partitioning and pin-multiplexing for co-modeling and in-circuit testing of large designs
Strategies and options to facilitate design debug
3rd-party IP considerations for FPGA implementation
Evaluating optimal prototyping performance vs. effort
Analyzing Design Compiler® scripts to determine constraints
Configuring hardware clocking resources
Communication with high-level test benches
Utilizing co-simulation for transactionbased interface standards such as SCE-MI 2.0

Upon the completion of this phase, examples of the ASIC-targeted design, mapped for the FPGA and CHIPit system, should be in place.

CHIPit Hardware Configuration
Once the flow is set up and the RTL design is ready for FPGA mapping, your engineers will get hands-on experience configuring the CHIPit system.

Additional Training (Optional)
Depending on your requirements, Synopsys consultants can augment the Jumpstart training in the following areas:

Certify® partitioning technology
Identify®, Identify Pro debugging
Synplify® Premier FPGA Synthesis
Certify Pin Multiplexing (CPM) to time-share I/O pins
Synplify Premier features for in-system debug and faster timing closure
In-depth hardware configuration and CHIPit custom daughter card considerations

Jumpstart Prerequisites

For more information about Synopsys products, support services or training, visit us on the web at: www.synopsys.com, contact your local sales representative or call 650.584.5000.

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