A common challenge in SoC design is that new RTL code for application-specific blocks has to be developed and tuned, then integrated with existing code that typically comes from multiple sources with varying degrees of quality. Achieving a high-quality RTL representation of the complete chip design is critical for ensuring the implementation will meet functional and performance requirements in a predictable manner.
As the provider of the world's most widely used IP cores and building block libraries, Synopsys is expert in the creation and integration of reusable IP blocks. Synopsys helped pioneer design reuse methodologies. In fact, we wrote the book.
Leveraging these disciplined IP development methodologies and our expertise with the DesignWare® IP portfolio, Synopsys Professional Services helps you rapidly and predictably migrate your design from RTL to GDSII. Our consultants will work with your design team to optimize the chip's micro-architecture, select and qualify IP, and then integrate the blocks into an optimized implementation. (For customers that implement proprietary subsystems in their SoCs, our expertise includes the creation of custom IP "wrappers" that interface industry-standard IP to your proprietary buses.)
Synopsys Professional Services also has significant expertise in implementing ARM®-based SoCs. Using the jointly developed ARM-Synopsys Reference Methodology, we provide licensees with fully modeled and validated IP cores that have been 'hardened' to the selected process technology.