Design Flow Deployment 

Optimize your SoC/ASIC design flow to address your latest chip design challenges  

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Today's nanometer design geometries put tremendous pressure on physical design teams to maintain advanced design flows to achieve any satisfactory level of predictability and productivity in the chip design process. Timing closure and design closure remain a major challenge, but power management and low power design challenges have become top tier issues as well, along with the increasingly interdependent effects of signal integrity, manufacturability and testability. ASIC design flows that were stretched to their limits to produce 130 or even 90 nanometer designs may not work at all at 65 and below without major enhancements.

Extensive experience with advanced physical designs, expertise with Synopsys' Galaxy™ and Discovery™ platforms, and significant investment in building and maintaining leading-edge EDA design flows in our own design centers, make Synopsys Professional Services uniquely capable of helping you optimize your design flow for the challenges of implementing and verifying even the most advanced ASIC designs.

Because we're Synopsys, we're continually monitoring new tool releases and applying their most advanced features to our leading customers' design flows. And since Synopsys co-developed the reference flows for many of the leading IP providers and foundries such as ARM, TSMC, IBM, Global Foundries, UMC, SMIC and Common Platform, we are the natural choice to customize and deploy them into your production design environment.

Now, with Synopsys' Lynx Design System, you can deploy a complete, tapeout-proven RTL-to-GDSII flow that helps you address both design- and project-related bottlenecks. Our SoC design consultants are experienced users of Lynx and can help you accelerate its deployment or customize it as necessary to meet your unique design environment requirements.

Whether you're at the beginning or in the middle of your SoC or EDA or ASIC design project, whether you need a minor upgrade to your design flow or a complete production-ready design system to migrate to a new nanometer design node, Synopsys Professional Services will help you eliminate the bottlenecks that impact your design productivity.

Synopsys' Design Flow Deployment services include assistance with:

  • Assessment of your existing design flow, design environment and design methodology
  • Implementation of production-ready sub-flows for project-specific challenges - timing, signal integrity, low power, design-for-test, etc.
  • Deployment of complete design flows to ease ASIC-to-COT or new technology node migrations - 90nm, 65nm, 45/40nm, 32nm, 28nm, 22/20nm
  • Instantiation of customer-specific implementation methodologies such as hierarchical design or "virtual flat" design
  • Incorporation of new verification methods such as assertions, functional coverage, and testbench automation into an existing environment
  • Deployment and customization of the Lynx Design System for customer-specific design environments, methodologies and process nodes
  • Validation of a new design flow or sub-flow with a "pipe-cleaner" design and/or test chip

To get more information on how we can customize our EDA design services for you, please contact Synopsys Professional Services or call your local sales representative.



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