Webinars 

Increase FPGA Performance with Enhanced Capabilities of Synplify PRO and Premier
Timing is everything! Find out how to reproducibly improve FPGA performance results using Synplify Pro and Synplify Premier. This webinar includes tips on how to set up you FPGA design to achieve better timing results downstream, recommended techniques to analyze and tune design performance for faster timing closure and new "under the hood" Synplify Premier placement-aware logic synthesis technology that further boosts timing performance.
Paul Owens, Senior CAE, Synplify Business Group, Synopsys
May 06, 2014
 
Streamlining IP and Subsystem Prototyping with HAPS-DX
In this webinar we will introduce the new HAPS Developer eXpress (HAPS-DX) solution for complex IP and subsystem prototyping to accelerate IP and subsystem bring-up and streamline IP to SoC integration.
Neil Songcuan, Senior Product Marketing Manager, Synopsys
Jan 29, 2014
 
LTE and LTE-A MIMO Link Adaption Performance Optimization
Learn the link adaptation methods in LTE/LTE-A and present strategies for simulating and designing receivers to implement these methods.
John Lundell, R&D Manager, Synopsys
Dec 10, 2013
 
Debug and Bring-Up Automation for the HAPS-70 Series FPGA-Based Prototyping System
This webcast explores debug and bring-up automation features unique to the next-generation FPGA-based prototyping system, the Synopsys HAPS-70 Series.
Nathan Henderson, Corporate Applications Engineering Manager, Synopsys
Sep 26, 2013
 
Using FPGA-based Prototyping to Validate IP Integration Without Breaking a Sweat
Learn how to test DesignWare USB 3.0 interface IP and implement it on a HAPS FPGA-based Prototyping System. Review best practices on how to utilize Synopsys' Identify HW/SW tools to test the interface in the context of the larger chip design.
John Kuhns, Synopsys Professional Services, Senior Design Consultant
Jul 17, 2013
 
High-Throughput FPGA Signal Processing: Trends, Tips & Tricks for QoR and Design Reuse
Learn about best practices for creating high-throughput signal processing designs for FPGAs, with a focus on achieving quality of results and design reuse across FPGA devices, families, and vendors.
Chris Eddington, Sr. Technical Marketing Manager, Synopsys
Jul 09, 2013
 
Conquering HSPA+ Modem Design
To understand the design flow and provide an introduction to InterDigital’s HSPA+ modem IP.
William Lawton, Senior Manager, InterDigital Communications; Vafa Ghazi-Moghadam, Staff R&D Engineer, Synopsys
May 15, 2013
 
Case Study: Design and FPGA-Prototyping of an Application Specific Processor for Embedded Vision
This webinar introduces Synopsys’ Vision Processor Design and Prototyping solution, featuring Processor Designer and HAPS FPGA-prototyping.
Drew Taussig, Corporate Applications Engineer, Synopsys
May 07, 2013
 
Ease Debug and Control of Network Software Using Virtual Prototypes to Do Full System Simulation
Learn how you can use a virtual prototype with a DesignWare Gigabit Ethernet model and ARM Cortex-A processor models to simulate a network application like e.g. a server farm.
Robert Kaye, Technical Specialist, ARM; Tom De Schutter, Product Marketing Manager, Synopsys
May 02, 2013
 
Optimizing and Validating the Performance of Your AMBA®4 Interconnect
Learn how to use Synopsys Platform Architect to drive performance criteria that can now be verified in the functional verification process through tight integration with Synopsys Verification IP.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys; Tim Kogel, Solution Architect, Synopsys
Apr 25, 2013
 
10 ways to Debug your FPGA Design
Learn how to cut FPGA debug time with more effective diagnosis of FPGA design setup and design specifications, and by identifying design errors en-masse in a single iteration. If you are an ASIC designer, learn techniques to more quickly make your design "FPGA friendly" to get working FPGA implementation on the board.
Angela Sutton, Staff Product Marketing Manager, FPGA Implementation , Synopsys, Inc.
Feb 12, 2013
 
New FPGA-based Prototyping Solution: HAPS-70 Series - Best Practices
This webinar is intended for designers who are already prototyping their ASIC design or considering prototyping their next ASIC design. Learn about best practices and new HAPS-70 system technology.
Neil Songcuan, Senior Product Marketing, Synopsys
Feb 06, 2013
 
Accelerating Embedded Software Development for Renesas RH850 Microcontroller
Learn about the concepts of virtual prototyping and their application to the Renesas RH850 MCU family through the Renesas Velocity Lab and the Synopsys VDK for Renesas RH850 MCU.
Marc Serughetti, Director of Business Development, Synopsys; Martin Baker, Senior Manager, Ecosystem and Business Management, Renesas
Jan 31, 2013
 
Synopsys Vision Processor Starter Kit: Implementing Embedded Vision Applications Optimized for Power
This webinar introduces the new Vision Processor Starter Kit from Synopsys, featuring Processor Designer, the industry’s leading ASIP design tool.
Bo Wu, Technical Marketing Manager, Synopsys
Jan 16, 2013
 
LTE-Advanced Modems Coming to Life
This webinar will explain the steps that need to be taken at the different stages of the design process, and how these steps can be integrated into a complete design and verification flow.
Dr. Vafa Ghazi-Moghadam, R&D Engineer, Synopsys; Simon Ache, Product Manager, Rohde&Schwarz
Nov 08, 2012
 
Low Power Video Processing for the Mobile SoC
Learn how Synopsys Platform Architect is used to efficiently explore and optimize the HW-SW partitioning and mapping to get the most from Embedded GPUs.
Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys; Tim Kogel, Solution Architect, Synopsys
Oct 18, 2012
 
Debugging with Virtual Prototypes
Learn about the Lauterbach TRACE32 development tool and its seamless integration with Virtualizer, supporting a broad set of debugging capabilities for virtual prototypes.
Achim Nohl, Solutions Architect, Synopsys. Inc. Jerry Flake, Western Regional Sales/Support Manager, Lauterbach
Oct 11, 2012
 
Debugging Methods for FPGA-Based Prototypes - Best Practices for System Troubleshooting and RTL Debug
Learn about new methods and technology to increase the ROI of an FPGA-based prototype and expand its role for hardware/software validation.
Troy Scott, Product Marketing Manager, Synopsys
Sep 18, 2012
 
Early Optimization of Multicore SoC Architectures Using Synopsys' Platform Architect and Arteris FlexNoC
Learn how to efficiently explore and optimize the dynamic system performance of an Arteris FlexNoC based SoC design in SystemC using a mobile device case study example in Synopsys' Platform Architect.
Kurt Shuler, Vice President of Marketing, Arteris; Patrick Sheridan, Senior Staff Product Marketing, Synopsys; Tim Kogel, Solution Architect, Synopsys
May 15, 2012
 
LTE-A Physical Layer Design & Simulation
Learn about the LTE-Advanced standard (3GPP Rel.10), its main enhancements over LTE Rel.8 and their impact on the overall system performance.
Dr. Vafa Ghazi-Moghadam, Staff R&D Engineer, Synopsys Inc.
Mar 08, 2012
 
Faster, Safer Implementation of High-Reliability, High Availability Designs using FPGAs
Learn techniques on how to build high operation reliability into your FPGA designs in the face of radiation-induced errors in the field, and how to validate and trace the result of your design implementation before you deploy your FPGA-based system.
Angela Sutton, Staff Product Marketing Manager, FPGA Implementation
Jul 14, 2011
 
LTE Physical Layer Design: Basics
Overview of the LTE standard, LTE simulation library and Synopsys SPW algorithm design tool.
Bo Wu, Technical Marketing Manager, Synopsys
Sep 15, 2010
 
LTE Physical Layer Design: Optimization
Learn more about LTE physical layer design and how design choices can impact implementation and performance.
John Lundell, R&D Manager, Synopsys
Aug 18, 2010
 
LTE Physical Layer Design: Synchronization
Learn more about some of the features of the LTE User Equipment (UE) acquisition and synchronization process.
Louie Valena, Corporate Applications Engineer, Synopsys
Jul 21, 2010
 
Using Simulation to Implement a Robust Design Flow
Listen to our Robust Design Web Seminar to discover how Robust Design methodologies coupled with Synopsys' Saber simulation and analysis solution can improve your design performance and reliability for mechatronic systems.
Mike Jensen, Corporate Applications Engineer, Synopsys
Dec 10, 2006
 


NewsArticlesBlogsDatasheetsSuccess StoriesWhite PapersWebinarsVideosNewsletters