HAPS Daughter Board Datasheets   

 

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Interconnect System Components
HAPS to HAPS accessories

BIO1
The BIO1 contains LED indicators, push buttons and a USB port to support direct access to the design for debug purposes. The card is controlled via a GPIO header on a HAPS motherboard. Several BIO1 cards can be stacked together side-by-side to expand the number of I/O functions.

TERM-TOP_1x1 Termination Daughter Board
The TERM-TOP_1x1 is a termination board especially designed for terminating global buses between several motherboards in the HAPS-50 series. Termination boards are recommended on the first and last connector in the chain. Two of these boards are already included in HAPS-54 deliveries.

LAB_1x1A Daughter Board
The LAB_1x1A is perfect for small hand-built experiment designs, and also provides easy access to measure points for all signals in a HapsTrak II connector. The signals from the HapsTrak II connector are evenly spread out in two areas, one with a 2 mm grid and the other with a 0.1" grid.

STB2_1x1 Test Board
The STB2_1x1 is a board for testing purposes, used in combination with the self-tests for motherboards in the HAPS-50 series. With STB2_1x1, it is possible to detect open circuits as well as power and ground faults in any HapsTrak II connector.

CONF30 CompactFlash Configuration Daughter Board
The CONF30 configuration daughter board is used to configure the FPGAs on motherboards in the HAPS-30 and HAPS-50 series products from CompactFlash devices.


Adapters
Interface HAPS to other systems

CTI_2x2
The CTI_2x2 allows an ARM® Core Tile from the Versatile family to interface to a HAPS motherboard. The HAPS motherboard will effectively function as a custom base board for the Core Tiles. All peripherals can be implemented using boards from the HAPS family.

MICT_1x1
The MICT_1x1 board makes all signals in one HAPS connector available in four 38-pin Mictor connectors for easy access with a logic analyzer. It can be placed directly on the HAPS motherboard or stacked on a daughter board.

HAPS_ARM_VTE_PI Daughter Board
The HAPS_ARM_VTE_PI board is an interface between HapsTrak and a 320-pin PISMO (Platform Independent Storage MOdule) slot. It is designed to be used on an ARM Versatile Express LogicTile V2F-1XV5, thereby creating a link between a Versatile Express development board and a HAPS system.

HAPS-600 HapsTrak II Adapter
The HapsTrak II Adapter Board is a FPGA-extension board for the HAPS-600 system. It is intended to enable the usage of HapsTrak II compatible daughter boards on HAPS-600 and CHIPit Platinum systems.


I/O
Interfaces supporting standard protocols

USB3_HTII
The USB3_HTII is a HAPS daughter board providing a single port USB 3.0 physical layer interface. The daughter board supports USB 3.0 Device operation when utilized alongside the DesignWare USB 3.0 digital controller IP (sold separately) or other 3rd party controller IP.

High Speed I/O Virtex-6LXT Daughter Board
The High Speed IO Virtex-6LXT daughter board allows high speed interface standards such as PCIe Gen 2, SATA 6 Gbps, and Gigabit Ethernet to interface with the HAPS-60 or HAPS-50 systems. The High-Speed I/O board can be connected to the HAPS-60 series or HAPS-50 series systems as a daughter board through two standard HapsTrak II connectors. The High Speed IO board features the Xilinx Virtex-6 XC6VLX75T FPGA which includes 12 GTX transceivers to enable the support for high speed interfaces.

PCIE-1-KIT
The PCIE-1-KIT board is a one-lane PCI Express solution for HAPS, including: PCIE 1_1x1: 1-lane HAPS daughter board, PCIE-4_PC: 4-lane host interface board, and PCIE-4_CABLE: 4-lane cable, 1 meter in length.

DVI_1x1A
The DVI 1x1A board contains one DVI input channel, one DVI output channel, and one programmable clock oscillator. It provides a HAPS motherboard with a continuous real-time 24, 30, 36 or 48 bit parallel stream, and a regenerated clock for the DVI input. The DVI output is sourced by the motherboard with a continuous real-time 24, 30, 36 or 48 bit parallel data stream.

GEPHY_1x1
The GEPHY_1x1 board contains two Gigabit Ethernet PHY devices with fully featured physical layer transceivers that support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols. Two GEPHY_1x1 boards can be stacked to get four Ethernet channesl on a single HAPS connector.

DVB-OUT_1x1 SPI and ASI-C Interface Daughter Board
The DVB-OUT_1x1 implements the physical layer 0 of an SPI output (Synchronous Parallel Interface) and an ASI-C output (Asynchronous Serial Interface on coaxial cable), according to the standard EN 50083-9:1998.

ADC_1x1 Combined Analog/Digital Daughter Board
The ADC_1x1 is a combined analog-to-digital and digital-to-analog board with two high-speed (80 Msps) and two low-speed ADC channels, as well as two low speed DAC Channels. The high-speed ADC channels are designed for a wide variety of applications including SW radio adn IF/IQ demodulation.


Memory
Different kinds of memories

LCD1_1x1
The LCD1_1x1 board contains connectors for interfacing flat panel displays to a HAPS system. It is also equipped with four high speed RS-232 ports, one universal JTAG port, and one HAPS compatible GPIO port.

DDR3_HS_1x2
The DDR3_HS_1x2 HAPS daughter board contains nine DDR3 devices with a memory organization of 9 x 512M x 8bit that allows chip developers to interface ASIC/SoC designs with an external high capacity and high performance DDR3 memory module using HapsTrak II connectors. The DDR3 daughter board is targeted to run at a clock rate of 400MHz.

FLASH_1x1_HTII Daughter Board
The FLASH_1x1_HTII HAPS daughter board contains two 1Gbit NOR Flash PROMs, accessible as 8-bit or 16-bit wide words.

DDR3_1x2 Daughter Board
The DDR3_1x2 board is an interface between HapsTrak II and a 240-pin UDIMM (Unbuffered Dual Inline Memory Module) DDR3 SDRAM module.

MSDRAM_1x1 Daughter Board
The MSDRAM HAPS daughter board contains two independent ranks to provide a total capacity of 256 MBytes. A rank contains two MSDRAM (Mobile SDRAM) devices with 8M x 4 x 16bit (64 MByte) each.

DDR2_1x2_SODIMM_HTII Daughter Board
The DDR2_1x2_SODIMM_HTII daughter board is a 200-pin SODIMM DDR2_SDRAM module that allows chip developers to interface ASIC/SOC designs with an external high capacity and high performance DDR2 memory module using HapsTrak II connectors used with the HAPS-60 series.

DDR2_1x2 Daughter Board
The DDR2_1x2 HAPS daughter board is a 214-pin MicroDIMM DDR2-SDRAM module that allows chip developers to interface ASIC/SOC designs with an external high capacity and high performance DDR2 memory module.

SRAM_1x1_HTII
The SRAM_1x1_HTII board contains a synchronous SRAM subsystem. The memory is organized in 2Mx72bits. The default operation mode is Pipeline.



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