New Release of Synphony Model Compiler 2012.09
The new Synphony Model Compiler release, from Synopsys, introduces major new features for both the FPGA and ASIC flows. The new features include:
- New FIR2 block achieves high quality of results for multichannel, multirate filtering for digital radio upconverter and downconverter applications. The new block achieves results equivalent to hand-coded RTL, but automatically optimizes for Altera, Xilinx and ASIC targets. A new user interface and support for vector and matrix allows fast design capture and verification for large multi-channel digital radio hardware.
- New matrix support enables fast IP development of hardware accelerators for transforms, filterbanks, video, imaging, and other multi-dimensional signal processing. High-level synthesis optimizations make it possible to create a range of architectures that trade off area, speed, and power of matrix operations.
- New ASIC power analysis features allow rapid analysis of power for HLS-based architecture exploration. Features include integrated flows for Power Compiler/Design Compiler, DesignWare MinPower, Activity Data Generation, clock gating, and multi-clock optimization.
- RTL Encapsulation – embedding RTL into your Simulink model is now even easier with enhanced user interface and simulation speeds. RTLE supports multirate designs with synchronous and asynchronous clock domains and enables very high simulation performance while using interface IP, 3rd party IP, and legacy RTL IP in your Synphony Model Compiler designs.
- Synphony Model Compiler now generates hardware-accurate C-models that are up to 100X faster than RTL simulation. Wrappers can be automatically generated for running the C-models in Simulink, SystemC, Modelsim, VCS, and other C-based simulation environments.
- C-models of RTL can be generated using RTL Encapsulation blocks.
for the datasheet describing the new Synphony Model Compiler Release. Existing customers can find the release notes and downloads on SolvNet
White Paper – Integrating High-Level Synthesis Designs into SoCs with Less Effort and Risk
Multi-rate ASIC design can be tricky for many reasons which include the complications of using multiple clocks, the clock domain crossings (CDC) of signals in the design, and the programmable interfaces across the various clock domains, just to name a few. Furthermore, multi-rate datapaths have more HW architecture choices which can drastically impact power and area results. This webinar shows how to use Simulink high-level modeling as a front-end to ASIC design flows using Design Compiler and VCS, and to quickly create and explore multi-clock HW architectures while reducing verification time and effort.
App Note – Using C-Output to Speed Up Simulink Simulations
Synphony Model Compiler (SMC) lets you capture a design using model-based design entry in Simulink/MATLAB, and then synthesize architecturally-optimized, synthesizable HDL for the design. SMC also has unique technology that can generate a C-model for high-performance simulation in a variety of simulators like SystemC, Modelsim/VCS, or Simulink. By using this fast cycle-accurate model, one can actually achieve 3-10x simulation speedup over the original Simulink model, and up to 100x over RTL simulation, significantly improving productivity for hardware and system-level verification.
Customer Success: ST and Digital TV Tuners
This ST design team needed a way to speed up the development cycle for their digital IF TV demodulator IP core for 65nm ASIC. They used Synphony Model Compiler (SMC) to quickly create a high-level model of their algorithm, and then used SMC high-level synthesis tools to rapidly create FPGA prototypes and optimized architectures for their 65nm ASIC flow. SMC also increased reliability and productivity of their mixed-signal verification flow, including STARC-compliant RTL.