Synphony C Compiler for Wireless Applications  


Wireless communication is everywhere and will only become more ubiquitous -- we want to work and live without wires. There are more and more standards and increasing numbers of protocols to support. There are tremendous opportunities for those who can deliver low cost, low power, high quality solutions in a wide number of applications.

Design teams are faced with conflicting goals. On one hand, customers require higher performance, higher bandwidth, and support for multiple standards for content delivery. At the same time, area and power have to be minimized to reduce the solution cost and the end-device form factor. These conflicting goals open up a lot of room for innovation and differentiation.

Synphony raises the design abstraction level to C, the same untimed language commonly used during algorithm development. Synphony allows the designer to focus on the key differentiator – the algorithm and the overall architecture, while Synphony C Compiler takes care of the complex task of extracting parallelism and creating high performance hardware.

Typical Wireless Designs
Although the wireless market consists of multiple sub-areas such as cellular, wireless LAN, Bluetooth, and GPS with multiple standards in each area (e.g., CDMA, LTE, 802.11 a/b/n, WiMAX), they all require some of the same basic signal processing capabilities, which are ideally suited for Synphony C Compiler. Examples include:

  • Time/frequency domain transitions (FFT/IFFT)
  • Equalization and other filters, upsampling/downsampling
  • Interleaving/de-interleaving
  • Error coding and correction (Viterbi, Turbo, LDPC, etc.)
  • Channel coding and decoding

Customers are using Synphony C Compiler's unique capabilities to build wireless designs that are multi-rate, have complex hardware interaction and merge multiple modes and standards into a single design with excellent quality of results.

Demonstration Example
The following diagram shows a generic block diagram for an 802.11a transmitter/receiver. Synphony C Compiler was used to create the entire transmitter as a demonstration example. The details for this design can be presented and explained upon request.

Customer Case Study: LDPC Decoder
Synphony C Compiler was used to design a scalable and low power low-density parity-check (LDPC) decoder for a next generation wireless handset SoC. The flexible decoder fully supports the IEEE 802.16e WiMax standard. The generated RTL was synthesized using Synopsys Design Compiler using the TSMC 65nm, 0.9V CMOS technology. The results were as follows:

  • Maximum throughput: 415Mbps at 400 MHz clock frequency for maximum code length of 2304 at code rate 1/2
  • Area: 1.2 mm2
  • Peak power consumption: 180mW
  • 23.5% reduction in dynamic power by using the multi-level clock gating capability of Synphony C Compiler

When normalized to the same technology, this decoder achieves comparable or even better performance than the hand designs in terms of throughput, area, and power.

Customer Case Study: Prime Factor DFT
In this case, Synphony C Compiler was used to design a Discrete Fourier Transform (DFT) hardware accelerator used in a Long Term Evolution (LTE) transmitter for a high performance fourth generation cellular SoC.

The DFT specified in the standard is a combination of powers of 2m, 3n and 5l and is always divisible by 12. Since all the required LTE sizes are divisible by 12, the design was divided into two DFTs using the Cooley-Tukey technique. The first DFT performed a Q point DFT, where Q can range from 1 to 100. It is executed 12 times. The second transform performed a 12-point DFT and is executed Q times. The first DFT can be programmed for 1 out of 34 possible modes. The prime factor algorithm (PFA) was selected so that complex multiplications can be substituted by address permutations that translate to ROM accesses.

The design called for specialized units to perform DFTs of sizes 2m, 3n and 5l. These were coded as separate C functions, verified independently and synthesized to TCABs, and then integrated within the complete design. The design was verified on an FPGA prototype platform and was ready for an ASIC implementation. The area/performance/power results were comparable to hand-coded design.

Other Representative Designs
  • HSDPA Frequency Domain Equalizer (FDE)
    • Complex, high-performance multi-block design with an area of ~400k gates
    • 2 month design cycle vs. >9 months for manual design
  • MIMO decoder: Multiple designs with various performance points
  • 3GPP Crypto Engine
    • Kasumi based security algorithm consisting of 3 blocks
    • High performance target: 1.1 GBit/s at 166 MHz
  • Configurable filter chain for 2.5G low cost receiver
  • Multimode filter for Bluetooth audio optimized for low power and area: 1 week to create C code & verified RTL
  • BCH ECC for Flash memory: Completed in ~2 weeks with 40% smaller area than off-the-shelf IP

    Low Power Design
    Power consumption is the most critical differentiator for wireless designs, and designers struggle to indentify where power is being consumed and how to reduce the power consumption. Synphony C Compiler provides advanced capabilities for power optimization at the system level using a variety of techniques at the system and architecture level.

    Automatic multi-level clock gating
    Designers can use Synphony C Compiler to automatically insert multi-level clock gating along with the necessary control logic. Insertion of the clock gating and its functional verification is fully automated and easy to use, eliminating a lot of time-consuming manual effort. The result is significant power savings:

    • 22.4% power reduction in dynamic power for a customer wireless design
    • The LDPC decoder design described above achieved 23.5% reduction in dynamic power over an identical design using a standard flow
    • Eight complex applications in video, imaging and wireless domains demonstrated the following:
      • Up to 50% reduction in dynamic power for executing a single task and up to 30% savings while executing a large number of tasks
      • Average power reduction of 22% for a single task and 15% over multiple tasks

    These power savings are over-and-above what can be achieved with the gate-level clock gating in down-stream tools.

    Design Exploration for Low Power Design
    Designers can use Synphony C Compiler to easily explore multiple implementations, trading off power and area. The figure shows multiple implementations of a wireless design with a specified throughput but running at different frequencies. To keep the throughput constant, lower frequencies require design to operate at a higher parallelism. The 1x, 2x, 4x and 8x in the diagram show how much parallelism is built into the hardware.

    Exploring multiple implementations and trade of power and area using Synphony C Compiler.

    The 40 MHz design has ~37% less total (dynamic + static) power consumption than the 320 MHz design. Since power consumption is linearly dependent on frequency and area, it is not at all obvious why that is the case. The reason is that, in practice, the area increase is not linear – that is, the 40 MHz design is not 8 times as big as the 320 MHz design. Using Synphony C Compiler, it took less than a day to implement all these four designs – something, that would have been completely impractical if these designs were done manually.