New Release of Synphony Model Compiler 2011.09
The new Synphony Model Compiler release, from Synopsys, introduces major new features for both the FPGA and ASIC flows. The new features include:
- RTL Encapsulation – you can now embed RTL in your high-level model and simulate the complete system in Simulink without the need of external simulators. This enables very high simulation performance while using interface IP, 3rd party IP, and legacy RTL IP in your Synphony Model Compiler designs.
- 10 new IP blocks: including Cyclic Redundancy Check (CRC), Pseudo-Noise Generators, and more.
- New IP Optimizations: FIR now has an additional architecture choice which has significant area and performance improvements on certain target technologies, especially ASIC.
- High-level synthesis optimization controls are now available for Folding and Pattern Folding.
- HLS Subsystem block has some QoR and usability enhancements.
for the datasheet describing the new Synphony Model Compiler Release. Existing customers can find the release notes and downloads on SolvNet
Recent Webinars and Success Stories:
Using High-Level Synthesis to Streamline ASIC Multi-Rate Communications Design
Multi-rate ASIC design can be tricky for many reasons which include the complications of using multiple clocks, the clock domain crossings (CDC) of signals in the design, and the programmable interfaces across the various clock domains, just to name a few. Furthermore, multi-rate datapaths have more HW architecture choices which can drastically impact power and area results. This webinar shows how to use Simulink high-level modeling as a front-end to ASIC design flows using Design Compiler and VCS, and to quickly create and explore multi-clock HW architectures while reducing verification time and effort.
Customer Success: ST and Digital TV Tuners
This ST design team needed a way to speed up the development cycle for their digital IF TV demodulator IP core for 65nm ASIC. They used Synphony Model Compiler (SMC) to quickly create a high-level model of their algorithm, and then used SMC high-level synthesis tools to rapidly create FPGA prototypes and optimized architectures for their 65nm ASIC flow. SMC also increased reliability and productivity of their mixed-signal verification flow, including STARC-compliant RTL.
Introduction to High-Level Synthesis for Multi-Rate Communications Design
This webinar shows how high-level synthesis optimizations can be used to more easily create efficient hardware architectures for multi-rate communications FPGA and ASIC designs. It illustrates how to you can use SMC to explore tradeoffs while keeping the multi-rate algorithm development simple. Wireless communications designs for FPGA and ASIC are used to illustrate the concepts.