SPW 

Overview 

Implementing complex digital signal processing systems for consumer, infrastructure, medical, automotive and aerospace and defense companies is the key challenge for innovation, since most of the design time is spent on investigating the effects of individual implementation decisions on the performance of the entire system. Pure language based approaches (MATLAB algorithms or C/C++) fail at these challenges as they do not constrain the modeling approach enough to improve implementation and simulation productivity.

Synopsys SPW provides a rapid path from innovation into implementation for digital signal processing systems. At its core is the C data flow (CDF) modeling paradigm which enables the most efficient description of digital signal processing algorithms which may be implemented in dedicated digital hardware or embedded software. CDF is an intuitive way of describing highly parallel systems which can produce a fully deterministic execution schedule, critical for the design of today’s heterogeneous, multicore architectures. The SPW signal processing algorithm tool is supported by an extensive set of DSP model libraries, with more than 3,000 models included in the base configuration at no additional cost.

Benefits
  • Faster innovation via model-based design for digital signal processing based products
  • More than 3,000 models included, all in source code
  • Filter-design system for the interactive design, simulation and analysis of FIR and IIR filters
  • Standard-compliant end-to-end systems configurations for a large number of communications and multimedia standards
  • Reduction of design effort by modeling with CDF
  • Drastic design cost reduction through systematic reuse
  • RTL co-simulation interface included in the base package
  • Proven hardware implementation path using the optional Hardware Design System (HDS)

Fig 1: SPW's model-based design concept delivers excellent design efficiency
Figure 1: SPW's model-based design concept delivers excellent design efficiency by providing a development environment with both graphical and language abstractions that captures the entire system in a hierarchical fashion

Available Options
  • Hardware Design System
Available Add-On Libraries
  • LTE/LTE-A Library
  • LTE Model Library for Xilinx IP



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