S2S Verification Overview Video

High-level overview of the Systems to Silicon Solution with David Park
David Park, Solutions Manager, Synopsys

S2S Verification Video

Interview with Rajiv Maheshwary and Janick Bergeron
Janick Bergeron, Scientist, Synopsys, Inc.; Rajiv Maheshwary, Senior director, Synopsys, Inc.

Customer Highlight

ST meets AMS simulation criteria with VCS-MX and CustomSim
Yuval Shay, Staff Engineer, Mixed-Signal Verificatin

SNUG San Jose 2010: Functional Verification Vision Session

In this session, Synopsys Fellow Janick Bergeron shares his vision on verification for the coming decade. Although many challenges and principals remain the same as they have for the last 20 years, the approaches to address them change due to the economics of IC design and development. By drawing upon past and current trends, future approaches to these verification challenges are highlighted and discussed.
Janick Bergeron, Fellow, Synopsys

DesignCon 2010: VCS Named DesignVision Award Finalist

Following the annoucement that VCS was honored as a finalist in the 2010 DesignVision Awards, Swami Venkat, Sr. Director of Verification Marketing at Synopsys, discusses the latest innovations within Synopsys' industry-leading functional verification solution at Designcon 2010.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys

DAC 2009: Solutions for Tough Verification Challenges

Synopsys hosted a special VCS Verification Luncheon event at DAC in San Francisco, CA focused on the VCS functional verification solution. Verification R&D experts from leading companies discussed how they leverage VCS’s multicore performance, transaction-based verification, tight mixed-signal integration, comprehensive low power verification capabilities and proven methodologies to solve today’s toughest verification challenges.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys; YC Wong, Director of IC Engineering, Broadcom; Shrenik Mehta, Sr. Director of Frontend Tools and OpenSPARC, Sun Microsystems; Faisal Haque, Director of Engineering, Qualcomm; and Amit Chowdhry, Member of Technical Staff, AMD

VMM User Forum Lunch Event: NVIDIA

Engineering the APX2500: Verification Methodology for Low Power Watch a presentation on NVIDIA's experience using the Verification Methodology for Low Power Design on the APX2500, the world's lowest power, high definition video and graphics computer on a chip.
Soma Bhattacharjee, Director of Engineering

VMM User Forum Lunch Event: Renesas Technology Corporation

Low Power Verification User Experience See a presentation on the unique challenges of low power design verification and how they are being addressed by Reneses using Synopsys' tools.
Yoshio Inoue, Chief Engineer


VMM User Forum Lunch Event: ARM, Ltd.

Need for a Low Power Verification Methodology. Learn about ARM and Synopsys' joint efforts to develop a Verification Methodology for Low Power Designs.
Alan Hunter, Verification Methodology Lead

VMM User Forum Lunch Event: IBM

"Are We There Yet?" Listen to a discussion on VMM Planner and how IBM used it on their BIST project to determine when they had run enough random tests.
Nancy Pratt, BIST Verification Lead