Technical Papers 

Are We There Yet
How do you know when you have run enough random tests? A constraint-driven random environment requires comprehensive coverage data, which often leads to information overload. Without an automatic way to associate pieces of coverage data with a particular feature-set in the test plan, the coverage report is only meaningful to the creator of the data.
Nancy Pratt Dwight Eddy

Debugging Embedded Software Using Virtual Prototypes
Virtualization of Electronic Systems plays an increasingly important role for the design of today’s complex electronic systems. This article introduces the usage and benefits of Virtual Prototypes for debug and analysis during embedded software development.
Achim Nohl, Solution Architect, Synopsys, Inc.

Efficient Design and Verification of Digital Communication Systems
LTE and WiMAX are key contenders for next generation mobile phone system. Both standards are excellent examples to highlight the huge complexity involved in modern communication algorithms. This increasing complexity is the trigger for new design methodologies and tools. This white paper provides a detailed analysis on the elements that determine algorithm design and verification efficiency for LTE and WiMAX communications systems. The concept of efficiency is discussed for modeling, simulation, reuse, and verification. Different methodologies and simulation solutions are then compared, providing the reader with specific algorithm design requirements.
Markus Willems, Ph.D., Product Marketing Manager, Synopsys and Holger Keding, Ph.D., Corporate Application Engineer, Synopsys.

High-performance, Parallel Simulation with VCS Multicore Technology
This white paper provides a detailed overview of VCS multicore technology, which improves verification performance by taking advantage of advances in the compute infrastructure. VCS multicore technology cuts verification time in half by harnessing the power of modern multicore CPUs and allows designers to identify performance bottlenecks and distribute time-consuming activities across multiple cores for faster functional verification and debug. Automatic partitioning and load balancing, event synchronization and memory optimization make VCS multicore unique for high-performance functional verification. Multicore technology combines the speed-up from parallel computation with the industry-leading Native Testbench (NTB) compiler optimization technique to deliver unmatched verification performance for large-scale designs for chip-level and system-level verification.
Usha Gaira and Sanjay Sawant

Pain Killers for the Fixed-Point Design Flow (Chinese)
Download Chinese-translated version
Holger Keding, Ph.D., Corporate Application Engineer, Synopsys GmbH, Germany

Pain Killers for the Fixed-Point Design Flow
In this article the challenges of different fixed-point design flows are presented, such as using native integral data types of the host machine to represent fixed-point data, or to use dedicated fixed-point types along with their operations and casting modes. The advantages and disadvantages of these flows are discussed, and how System Studio’s fast fixed-point optimization manages to combine the best of these two approaches to a solution that offers both, high simulation speed and excellent support for modeling and debugging.
Holger Keding, Ph.D., Corporate Application Engineer, Synopsys GmbH, Germany

SystemVerilog for e Experts
This document identifies the major differences between the e language as defined by the IEEE P1647/ D6 draft standard and the SystemVerilog language as defined by the IEEE Std. 1800™ 2005 standard. It explains the semantics of those differences and, where relevant, presents how similar functionality can be obtained using SystemVerilog.
Janick Bergeron Synopsys Scientist

Utilizing Digital Techniques for Analog and Mixed-Signal Verification
The ability of CustomSim to co-simulate with Synopsys' VCS digital simulator opens up the possibility of a "best of both worlds" approach enabling the majority of the chip to be simulated in the digital domain while the FastSPICE tool handles the analog blocks. Using this mixed-signal approach, many techniques and philosophies that are common in the digital world can be applied to the verification of mixed-signal systems.
Andy Milne, Application Consultant, Synopsys, Inc.; Damian Roberts, Application Consultant, Synopsys, Inc.