Webinars 

FineSim Technology for Analog and Full-Chip Simulation - A Micron Case Study
Learn about FineSim’s transient analysis advantage and the rich feature set that that combines SPICE and FastSPICE simulation technology in one single environment used for memory design at Micron.
Raed Sabbah, Sr. Design Engineer, Embedded Solutions Group, Micron Technology
May 08, 2014
 
Counting Down to 10 nm: GLOBALFOUNDRIES and Synopsys Perspective on Future Extraction
GLOBALFOUNDRIES and Synopsys will discuss the implications for extraction as foundries move to the next level of die shrink at 10nm.
Jongwook Kye, Fellow, GLOBALFOUNDRIES; Beifang Qiu, Senior R&D Manager, Synopsys
Apr 30, 2014
 
Accelerating Time to a Quality Floorplan: Cisco Systems and Synopsys Share Their Insights
Learn how IC Compiler’s new Data Flow Analysis (DFA) technology enables designers to accelerate time to a quality floorplan. Cisco Systems shares their experiences deploying this technology on a 100+ million gate ASIC to reduce floorplanning iterations with ASIC vendors and quickly identify and validate macro placement for the best quality of results.
Krishna Kumar Gundavarapu, Technical Leader, Cisco; Steve Kister, Technical Marketing Manager, Synopsys
Apr 23, 2014
 
Easy and Intuitive Analysis of Design Metrics with the Lynx Design System's QoR Viewer
Immediate access to pertinent design metrics enables better design decisions and faster time to results. Learn how Lynx enables you to customize metric review to highlight key data material to achieving design goals.
Aditya Ramachandran, Lynx Design System Staff CAE, Synopsys
Feb 19, 2014
 
Fastest Multi-scenario Timing Closure with PrimeTime Physically-aware ECO - AMD Shares Results (Simplified Chinese)
AMD and Synopsys will discuss the latest enhancements to PrimeTime's ECO Guidance technology to accelerate multi-scenario timing closure.
James Wai, Director of Physical Design, AMD; Chung Yang, Staff CAE, Synopsys
Dec 19, 2013
 
Fastest Multi-scenario Timing Closure with PrimeTime Physically-aware ECO - AMD Shares Results (Traditional Chinese)
AMD and Synopsys will discuss the latest enhancements to PrimeTime's ECO Guidance technology to accelerate multi-scenario timing closure.
James Wai, Director of Physical Design, AMD; Chung Yang, Staff CAE, Synopsys
Dec 19, 2013
 
Putting the Smarts into Smart Things - Designing ICs for the Internet of Things
Learn about the trends and challenges designers face when designing next-generation MCUs, and the latest Synopsys design and implementation tool technologies with proven DesignWare IP solutions.
Andy Biddle, Solutions Marketing Manager, Synopsys
Dec 17, 2013
 
Eliminate DDR3 Timing Errors with HSPICE and Zuken Constraint-based PCB Routing
Learn how to analyze signal integrity of critical traces in your PC board layout, incorporate board parasitics and define design constraints to eliminate timing violations.
Griff Derryberry, Applications Engineer, Zuken USA; Hany Elhak, Product Marketing Manager, Synopsys
Dec 11, 2013
 
Fastest Multi-scenario Timing Closure with PrimeTime Physically-aware ECO - AMD Shares Results
AMD and Synopsys will discuss the latest enhancements to PrimeTime’s ECO Guidance technology to accelerate multi-scenario timing closure.
Rajit Seahra, Senior Fellow, AMD; Vivek Ghante, Senior Corporate Applications Engineer, Synopsys
Oct 31, 2013
 
GLOBALFOUNDRIES and Synopsys Share Signoff Best Practices for 20/14-nm - Simplified Mandarin
This webinar will outline the essential elements of an effective advanced node signoff flow with PrimeTime and StarRC.
Adrian Au-Yeung, Member of Technical Staff, GLOBALFOUDARIES; James Chuang, Technical Marketing Manager, Synopsys
Oct 29, 2013
 
GLOBALFOUNDRIES and Synopsys share signoff best practices for 20/14-nm - Traditional Mandarin
This webinar will outline the essential elements of an effective advanced node signoff flow with PrimeTime and StarRC.
Adrian Au-Yeung, Member of Technical Staff, GLOBALFOUDARIES; James Chuang, Technical Marketing Manager, Synopsys
Oct 29, 2013
 
Enabling High-Frequency Clock Design: Imagination Technologies and Synopsys Share Their Perspectives
Imagination Technologies discusses their high frequency design requirements and clock design strategies and Synopsys presents clock implementation technologies available in IC Compiler that boost performance, including the new concurrent clock and data optimization capability.
Stuart Vernon, Director of Physical Design, Imagination Technologies Limited; Sumit Roy, Group Director of R&D, IC Compiler, Synopsys
Oct 24, 2013
 
Achieving Faster Design Closure on Imagination Technologies' GPU Core using Lynx Design System
Learn how to achieve faster design closure for a complex graphics core using Synopsys’ Lynx technology plug-in for Imagination Technologies' PowerVR Series6 GPU core by leveraging the exploration and feasibility analysis capabilities of Synopsys Design Compiler and IC Compiler.
Chad Gamble, Lynx Design System CAE, Synopsys
Oct 09, 2013
 
Power Management ICs – Efficient Design: A Richtek and Synopsys Perspective
Richtek and Synopsys present the key challenges and trends with latest power management Integrated Circuits and discuss recent EDA tool innovations to shorten development time and maximize QoR.
K C Chang, Vice President, Technology Development, Richtek Technology Company; Andy Biddle, Solution Marketing Manager, Synopsys
Oct 03, 2013
 
GLOBALFOUNDRIES and Synopsys Share Signoff Best Practices for 20/14-nm Design
This webinar will outline the essential elements of an effective advanced node signoff flow with PrimeTime and StarRC.
Dr. Tamer Ragheb, SMTS CAD Engineer, GLOBALFOUNDRIES; Dr. Ayhan Mutlu, Sr. Manager, Corporate Applications Engineer, Synopsys
Jul 31, 2013
 
Advanced-node Custom Layout Using the Laker Custom IC Solution
Learn about Laker’s rule-based layout, schematic-driven layout, and pattern-based multi-device layout features--ideal solutions for those seeking to improve custom layout productivity at 20-nm and below.
Neel Gopalin, Corporate Applications Engineer, Synopsys; Christopher Shaw, Senior Staff Technical Marketing Manager, Synopsys
May 30, 2013
 
Samsung Foundry and Synopsys Discuss Enabling 14-nm FinFET Design
Samsung Foundry and Synopsys present the challenges and opportunities of manufacturing with Samsung's 14-nm FinFET process and how these changes impact design enablement.
Dr. Kuang-Kuo Lin, Director, Foundry Design Enablement, Samsung Semiconductor Inc. (SSI); Dr. Henry Sheng, Senior Director of R&D, Synopsys
May 28, 2013
 
Late-Stage Leakage Recovery using the Lynx Design System
The rate of increase in SoC design complexity continues to challenge even the most experienced design teams. Synopsys’ Lynx Design System can help manage many of these complexities. This webinar will discuss strategies that leverage Final Stage Leakage-Power Recovery (FSLR) in IC Compiler, the new PrimeTime ECO Leakage flow and multi-channel libraries to recover leakage power late in the design cycle. These methodologies, as a part of a complete RTL-to-GDSII design solution available in Lynx, can help you achieve your power targets while maintaining design performance. These capabilities will be shown live in a short demo.
Devin Bright, Synopsys
May 08, 2013
 
Reducing Multi-mode STA Turnaround Time with PrimeTime Mode Merging - LSI Case Study
This webinar will introduce new PrimeTime technology to help design teams manage scenario increases by merging modes. LSI will discuss how PrimeTime mode merging allows them to reduce timing analysis.
Harish Aepala, Principal Methodology Engineer, LSI; Srinivas Muddagowni, Corporate Applications Engineer, Synopsys
Mar 27, 2013
 
Recover Leakage and Maintain Signoff Timing Using PrimeTime ECO - Simplified Mandarin
This webinar will introduce new PrimeTime ECO technology designed to reduce leakage power while maintaining signoff QoR. We’ll share customer data from Samsung and STMicroelectronics.
Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys; James Chuang, Technical Marketing Manager, Implementation Group, Synopsys
Mar 12, 2013
 
Recover Leakage and Maintain Signoff Timing Using PrimeTime ECO - Traditional Mandarin
This webinar will introduce new PrimeTime ECO technology designed to reduce leakage power while maintaining signoff QoR. We’ll share customer data from Samsung and STMicroelectronics.
Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys; James Chuang, Technical Marketing Manager, Implementation Group, Synopsys
Mar 12, 2013
 
Recover Leakage and Maintain Signoff Timing – with Customer Case Studies
This webinar will introduce PrimeTime ECO technology designed to recover leakage power, without introducing timing violations. We’ll share customer data that shows leakage power recovery up to 40%.
Rupesh Nayak, R&D Manager, Synopsys; Sasan Absalan, Corporate Applications Engineer, Synopsys
Jan 29, 2013
 
Accelerate Design Closure with PrimeRail In-Design Rail Analysis
Hear how to use PrimeRail’s In-Design Rail Analysis within IC Compiler to help you identify problems early in the design cycle and achieve faster design closure.
Jason Binney, Priciple CAE, Synopsys
Jan 23, 2013
 
Proven Techniques for Hierarchical Design Complexity using Lynx (Simplified Chinese)
You will learn about advanced f techniques within Synopsys' IC Compiler and Lynx Design System to manage hierarchical design complexity.
Ziyu Wu, Corporate Application Engineer, Lynx Design System, Synopsys
Jan 21, 2013
 
Reducing Design Margins Using PrimeTime Advanced OCV - Simplified Mandarin
Learn how designers are using Advanced OCV to speed design closure by eliminating overly pessimistic violations, and hear about customer and foundries’ deployment and support model for this technology.
James Chuang, Technical Marketing Manager, Implementation Group, Synopsys
Dec 12, 2012
 
Reducing Design Margins Using PrimeTime Advanced OCV - Traditional Mandarin
Learn how designers are using Advanced OCV to speed design closure by eliminating overly pessimistic violations, and hear about customer and foundries’ deployment and support model for this technology.
James Chuang, Technical Marketing Manager, Implementation Group, Synopsys
Dec 12, 2012
 
Double Patterning Ready Extraction and Signoff: TSMC and Synopsys Update
Learn how double patterning technology (DPT) has emerged as a critical technique to ensure printability of device and interconnects layers in IC manufacturing.
Anderson Chiu, Technical Manager, TSMC; Beifang Qiu, Senior R&D Manager, Synopsys
Dec 05, 2012
 
Double Patterning Ready Extraction and Signoff: TSMC - Simplified Mandarin
Learn how double patterning technology (DPT) has emerged as a critical technique to ensure printability of device and interconnects layers in IC manufacturing.
Anderson Chiu, Techincal Manager, TSMC; Beifang Qiu, Senior R&D Manager, Synopsys
Dec 05, 2012
 
Double Patterning Ready Extraction and Signoff: TSMC and Synopsys Update - Traditional Mandarin
Learn how double patterning technology (DPT) has emerged as a critical technique to ensure printability of device and interconnects layers in IC manufacturing.
Beifang Qiu, Technical Manager, Synopsys; Anderson Chiu, Senior R&D Manager, TSMC
Dec 05, 2012
 
Samsung and Synopsys Share Multicorner-Multimode Perspectives
This webinar highlights strategies for dealing with the large number of scenarios in the physical implementation flow. Samsung Semiconductor Inc. shares their experience using the IC Compiler- based MCMM solution to successfully meet their aggressive design objectives and Synopsys shares its multicorner-multimode (MCMM) design solution for addressing variability and design complexity at advanced technology nodes.
Santhosh Pillai, Senior Engineering Manager, Samsung, San Jose (SSI); Thomas Andersen, Director of R&D, IC Compiler, Synopsys
Oct 31, 2012
 
Accelerate Time-to-Tapeout with IC Compiler Custom Co-Design
Learn how using IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development.
Christopher Shaw, Senior Staff Technical Marketing Manager, Synopsys; Randy Bishop, Principal Engineer, Synopsys
Oct 24, 2012
 
Accurate Early Stage Power Estimation with PrimeTime PX: The NVIDIA Experience
In this webinar we will review the need for early power analysis, and show how useful power estimates can be achieved even with early and/or incomplete data. NVIDIA will outline their strategies.
Miodrag Vujkovic, Senior ASIC Design Engineer, NVIDIA; Maria Tovey, Corporate Applications Engineer, Synopsys
Oct 04, 2012
 
FinFET Process Modeling and Extraction at 16-nm and Below
Synopsys' R&D will discuss the motivation behind FinFETs and describe how Synopsys is driving the collaboration with major foundries to develop a next-generation extraction solution.
Bari Biswas, Senior Director R&D, Synopsys
Sep 27, 2012
 
Proven Techniques for Hierarchical Design Complexity using Lynx
In this webinar, you will learn about advanced flows and techniques available with Synopsys' IC Compiler and Lynx Design System to manage hierarchical design complexity.
Lydia Lee, Application Engineer, Synopsys Inc.
Sep 26, 2012
 
Save Weeks Fixing ECOs with PrimeTime (Simplified Mandarin)
Learn how PrimeTime Next-Generation ECO guidance automatically fix DRC, setup and hold violations to reduce iterations and shorten ECO fixing turn-around time.
James Chuang, Synopsys
Sep 26, 2012
 
Save Weeks Fixing ECOs with PrimeTime (Traditional Mandarin)
Learn how PrimeTime Next-Generation ECO guidance automatically fix DRC, setup and hold violations to reduce iterations and shorten ECO fixing turn-around time
James Chuang, Synopsys
Sep 26, 2012
 
5X Faster PrimeTime Multivoltage Timing Signoff: A Renesas Case Study
Learn how PrimeTime’s new multivoltage aware analysis technology reduces risk and speeds signoff for designs with multiple voltage domains, and how Renesas has successfully deployed it to reduce signoff turnaround time by 5X.
Francis Cheung, Senior Staff Engineer, EDA Engineering, Engineering Unit , Renesas Electronics America, Inc.; Carol Scemanenco, Senior Staff Engineer, Implementation R&D Group, Synopsys, Inc.
Jul 31, 2012
 
High-Productivity Analog Verification and Debug with CustomSim and CustomExplorer Ultra
See how Synopsys' advanced analog verification solution can dramatically increase your verification productivity with CustomExplorer Ultra, along with CustomSim and CustomSim-VCS.
Duncan McDonald, Product Marketing Manager, Synopsys
Jul 11, 2012
 
Faster Timing Closure with the Lynx Design System
Using the Lynx Design System, you will learn how to leverage the advanced timing closure features available with Synopsys’ IC Compiler and PrimeTime.
Aditya Ramachandran, Lynx CAE, Synopsys
May 09, 2012
 
Faster PrimeTime Signoff - Tips, Tricks and New Technology
Learn how to achieve a 2X reduction in signoff TAT, and build the expertise to create high-performance signoff scripts.
Tzong-Maw Tsai, CAE Director, Synopsys; Amrita Sahoo, Senior Corporate Applications Engineer, Synopsys
Apr 25, 2012
 
Streamlining Your ECO Flow For Fastest Setup, Hold and Timing DRC Closure
Learn what’s new with timing-aware DRC guidance for ECOs and which design flow and tool settings provide the fastest timing closure at 28 nm and below.
Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys; Vivek Ghante, Staff Corporate Applications Engineer, Implementation Group, Synopsys
Mar 14, 2012
 
Managing Hierarchical, Low Power Design Challenges with the Lynx Design System
In this seminar, we will demonstrate silicon-proven methodologies to describe power intent with IEEE 1801 (UPF) using a hierarchical design flow to address power consumption and design size concurrently. We will walk you through some of the key steps in implementing and analyzing a hierarchical design using UPF for both bottom-up and top-down Synopsys Galaxy-based flows.
Chad Gamble, Synopsys
Jan 17, 2012
 
Understand and Avoid Electromigration (EM) & IR-drop Effects in Custom IP Blocks
Learn how process technology & changing design styles increase the impact of EM & IR-drop effects on the performance/reliability of AMS, memory & custom digital IP blocks at 28nm and below.
Bradley Geden, Solution Architect, Synopsys
Oct 26, 2011
 
Faster Clock Analysis and Debug
Learn how to save time using Galaxy Constraint Analyzer and PrimeTime to ensure clean clock constraints and keep clocks free of timing violations during signoff.
Karen Linser, Staff Corporate Applications Engineer, Implementation Group, Synopsys; Robert Landy, Staff Corporate Applications Engineer, Implementation Group, Synopsys
Oct 25, 2011
 
Use IC Compiler and Custom Designer to Shave Weeks Off Your SoC Development Cycle
Learn how the seamless integration between IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits at any stage of development.
Chris Shaw, Sr. Technical Marketing Manager, Synopsys; Denis Goinard, CAE Manager, Synopsys
Oct 19, 2011
 
Save Weeks Fixing ECOs with PrimeTime and IC Compiler
See how design teams are saving weeks during implementation and signoff. Learn how PrimeTime Next-Generation ECO guidance and IC Compiler automatically fix DRC, setup and hold violations to reduce it.
Troy Epperly, Staff Engineer, CAE, Implementation Group, Synopsys; Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys
Jul 20, 2011
 
Optimize in Less Time: Rapid Design Exploration with Lynx Design System
Every SoC design requires a unique implementation strategy to navigate the tradeoffs between power, performance and area to achieve the best results for the specific use.
Aditya Ramachandran, CAE, Lynx Design System, Synopsys
Jul 19, 2011
 
Fast Timing Constraint Cleanup with Galaxy Constraint Analyzer
Learn how Galaxy Constraint Analyzer helps to produce signoff-quality timing constraints quickly, for even the most complex designs. Hear how AMD uses Galaxy Constraint Analyzer for quality assurance.
Richard Bishop, Member of Technical Staff, AMD; Karen Linser, Senor Corporate Applications Engineer, Implementation Group, Synopsys
May 18, 2011
 
Debug Timing Faster with PrimeTime Visualization Tools
Save time debugging complex timing paths during implementation and signoff using new visualization techniques in PrimeTime. See new clock and data analysis capabilities in action.
Robert Landy, Staff Corporate Applications Engineer, Implementation Group, Synopsys; Philip Cuney, Design Support Technical Leader, Design Support & Methodology Group, Home Entertainment & Displays, ST Microelectronics
Apr 20, 2011
 
Reducing Design Margins Using PrimeTime Advanced OCV – TSMC and User Views
Learn how designers are using PrimeTime Advanced OCV to speed design closure by eliminating overly pessimistic violations, and hear about TSMC’s views and support model for these new technologies.
Willy Chen, Program Manager, Design Methodology Division, TSMC; Norb Heindl, Senior Staff Engineer CAE, Implementation Group, Synopsys
Feb 23, 2011
 
Faster ECO Fixing Flows with PrimeTime and IC Compiler
This technical webinar will explain how IC Compiler and PrimeTime can be used to close timing during signoff. It will focus on the use of Distributed Multi-Scenario Analysis for automatic set-up and hold fixing, and will explain new PrimeTime 2010.06 DRC fixing capabilities. Attendees will learn how to minimize fixing run times, which approaches are best for closing setup and hold violations, and how to deploy SI fixing most effectively.
Uyen Tran, Director, CAE, Implementation Group, Synopsys; Jennifer Pyon, Senior Staff Engineer, CAE, Implementation Group, Synopsys
Jul 20, 2010
 
Eliminating Late-Stage DRC Surprises with In-Design Physical Verification
Third in the In-Design technology series featuring several high productivity in-design physical verification flows with IC Validator, including Automatic DRC Repair and Pre-Routing Verification – all from within IC Compiler.
Kerstin McKay, CAE Director, Physical Verification, Synopsys
May 05, 2010
 
Custom Designer: Advances in Custom Layout Automation with SmartDRD
SmartDRD technology visualizes, prevents and automatically fixes DRC violations to help designers quickly achieve DRC clean designs with significantly reduced effort.
Marc Swinnen, Sr. Product Marketing Manager, Synopsys; Christopher Shaw, Technical Marketing Manager, Synopsys
Mar 23, 2010
 
Reducing Design Margins Using PrimeTime Advanced OCV
How Advanced On-Chip-Variation works in comparison to flat-derate OCV and SSTA-based signoff technologies. Techniques for deploying PrimeTime to reduce pessimistic endpoints and slack pessimism.
Uyen Tran, Director CAE, Synopsys; Norb Heindl, Senior Staff Engineer, CAE, Synopsys
Feb 17, 2010
 
Addressing Signal Integrity Noise in Low Power Design
A discussion on the impact of low power design and the resulting requirements that drive the technologies in today’s static timing analysis tools. Learn about PrimeTime SI techniques that will enable you to deploy the SI noise-aware flow that best fits your needs for fast, accurate signoff.
Tzong-Maw Tsai, Director, Corporate Applications Engineer, Synopsys; Troy Epperly, Corporate Applications Engineer, Synopsys
Jan 20, 2010
 
HSPICE/Custom Designer for Analog & RF Circuit Design
Analog/RF design solution helps meet design challenges
Christopher Labrecque, HSPICE Marketing Manager, Synopsys; Fredrik Ivarsson, Custom Design Corporate Applications Engineer, Synopsys
Nov 05, 2009
 
Front-to-Back AMS Flow using Custom Designer
Follow the front-to-back development of an AMS block using Synopsys' Galaxy Custom Designer implementation solution.
Joe Mastroianni, VP of R&D, Les Spruiell, Product Marketing Manager, Synopsys; Chris Shaw, Technical Marketing Manager, Synopsys
Nov 03, 2009
 


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