Custom Compiler
Visually-assisted Automation

IC Validator
Signoff DRC/LVS tool architected and proven for in-design physical verification at leading-edge process nodes

PrimeTime Static Timing Analysis
Golden timing signoff solution and environment

StarRC Parasitic Extraction
Industry leading parasitic extraction for digital and custom design

DC Explorer
Early RTL Exploration Accelerates Synthesis and P&R

DC Ultra
Best-in-class timing, area and power QoR correlated with physical results

DC Graphical
Extends topographical technology to predict & alleviate routing congestion

Power Compiler
Provides complete solution for power synthesis & optimization

Ultra High compression for maximum test cost reduction

The industry's "gold standard" for accuracy, offers foundry-certified device models with state-of-the-art simulation and analysis algorithms.

High-performance, high-capacity FastSPICE simulation

Full-chip circuit-level simulation

TCAD Industry-Standard Process and Device Simulators

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