|Custom and Mixed-Signal Design Solution|
Synopsys’ unified solution for custom and cell-based design and verification provides a comprehensive, highly integrated suite of tools for advanced-node mixed-signal SoC design. The high degree of integration and interoperability shortens time-to-tapeout and improves design quality.
|Understand and Avoid Electromigration (EM) & IR-drop in Custom IP Blocks|
This whitepaper discusses the various trends exacerbating EM and IR-drop effects as well as design and analysis techniques to avoid them, and introduce Synopsys’ transistor-level analysis solution, which includes CustomSim for FastSPICE circuit simulation, StarRC for extraction, and Galaxy Custom Designer for custom layout.
Bradley Geden, Solutions Architect, Synopsys
|MOS Device Aging Analysis with HSPICE and CustomSim|
MOS Reliability Analysis (MOSRA) in HSPICE and CustomSim offers a robust and economic alternative
to empirical overdesign and extensive lifetime testing.
Bogdan Tudor, Joddy Wang, Weidong Liu, Hany Elhak, Synopsys
|Using Digital Verification Techniques on Mixed-signal SoCs with CustomSim and VCS|
A case study that explains the various aspects of a scalable and reusable methodology for verifying analog IP that can be applied to VMM/UVM, from verification planning to testbench implementation and coverage collection.
Graeme Nunn, Calvatec; Fabien Delguste, Adiel Khan, Abhisek Verma, Bradley Geden, Synopsys
|Accelerating Analog Simulation with HSPICE Precision Parallel Technology|
HSPICE Precision Parallel technology is a new multicore transient simulation extension to HSPICE for both pre- and post-layout of complex analog circuits such as PLLs, ADCs, DACs, SERDES, and other full mixed-signal circuits. HPP addresses the traditional bottleneck in accelerating SPICE on multicore CPUs with new algorithms that enable a larger percentage of the simulation to be parallelized, with no compromise in golden HSPICE accuracy. Additionally, efficient memory management allows simulation of post-layout circuits larger than 10 million elements.
Robert Daniels, Sr. Staff Engineer, Synopsys Inc.; Harald Von Sosen, Principal Engineer, Synopsys Inc.; Hany Elhak, Product Marketing Manager, Synopsys Inc.
|High-performance, Parallel Simulation with VCS Multicore Technology|
This white paper provides a detailed overview of VCS multicore technology, which improves verification performance by taking advantage of advances in the compute infrastructure. VCS multicore technology cuts verification time in half by harnessing the power of modern multicore CPUs and allows designers to identify performance bottlenecks and distribute time-consuming activities across multiple cores for faster functional verification and debug. Automatic partitioning and load balancing, event synchronization and memory optimization make VCS multicore unique for high-performance functional verification. Multicore technology combines the speed-up from parallel computation with the industry-leading Native Testbench (NTB) compiler optimization technique to deliver unmatched verification performance for large-scale designs for chip-level and system-level verification.
|Utilizing Digital Techniques for Analog and Mixed-Signal Verification|
The ability of CustomSim to co-simulate with Synopsys’ VCS digital simulator opens up the possibility of a “best of both worlds” approach enabling the majority of the chip to be simulated in the digital domain while the FastSPICE tool handles the analog blocks. Using this mixed-signal approach, many techniques and philosophies that are common in the digital world can be applied to the verification of mixed-signal systems.
Andy Milne, Application Consultant, Synopsys, Inc.; Damian Roberts, Application Consultant, Synopsys, Inc.
|SystemVerilog for e-Experts|
Synopsys' VCS® NTB Migration Services provide a low-risk path for users of the e language to achieve up to 5x faster performance with VCS Native Testbench (NTB) and the industry standard SystemVerilog language.
|Successful Mixed-Language Code Coverage with VCS|
VCS® provides industry-leading codecoverage
capabilities for Verilog, VHDL,
and mixed-language designs.
Vernon Lee, Principal Engineer,
Verification Group, Synopsys
|NanoSim: A Next-Generation Solution for SoC Integration Verification|
The convergence of consumer electronics and personal computing continues to drive the need for more powerful, complex and highly integrated IC design, fabricated with the latest manufacturing technologies.
Geoffrey Ying, Synopsys, Inc.,