Advanced Low Power Techniques Glossary  

 
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Adaptive Voltage Scaling (AVS)
A closed loop extension to Dynamic Voltage-Frequency Scaling. A power control functional block/monitor within the design scales voltage dynamically according to varying workloads. Process variation and temperature are taken into account as the monitor is on-silicon.

Back Biasing (See Well Biasing)

Clock Gating
Clock gating is a mainstream low power design technique targeted at reducing dynamic power by disabling the clocks to inactive flip-flops.

Dynamic Voltage and Frequency Scaling (DVFS)
Modifying the operating voltage and/or frequency at which a device operates, while it is operational, such that the minimum voltage and/or frequency needed for proper operation of a particular mode is used.

Isolation
Isolation is a technique for controlling the behavior of a signal that is driven into or out of a powered down power domain. Isolation consists of driving the signal to a known state -- 1, 0, or latching it to a previous value -- when the power domain is powered down.

Multi-Corner, Multi-Mode (MCMM) (also known as Multi-Scenario)
Multi-corner, multi-mode considers optimization at multiple operating corners, and in multiple operational modes, concurrently, instead of using an iterative process that may never converge.

Multi-Threshold CMOS (MTCMOS)
MTCMOS refers to a circuit scheme in which two types of transistors are used: low threshold voltage transistors capable of higher performance due to faster switching speeds, and high threshold voltage transistors that consume less leakage power. Coarse- and fine-grain MTCMOS refer to global and local sleep transistor allocation, respectively. The term "MTCMOS" is also commonly used interchangeably with the term "power gating". (See also Power Gating).

Multi-Voltage
Multiple voltage rail (multi-Vdd) can be supplied to a design to impact power and performance. A higher voltage yields a faster the circuit, but with higher the dynamic power. In many designs, only discrete portions of the design need to run at high speed. Other portions may only operate at lower speeds, and thus require lower voltages (and therefore consume less power).

Multi-Voltage Threshold (Multi-Vth)
An optimization performed to minimize leakage power by substituting cells that have higher voltage thresholds in place of cells that have lower voltage thresholds. Higher voltage threshold cells dissipate less leakage power, but operate slower than lower voltage threshold cells. Hence, multi-Vth optimization is a tradeoff between leakage power and path timing.

Power Domain
Power domains are areas in the design that are grouped by common power environments and power strategy, such as for power down conditions, operating voltage, power supply nets, etc.

Power Gating
Power gating uses high-Vth “sleep transistors” (also referred to as power switches) to disconnect power supplies to higher-speed and higher-power logic when that logic is not being actively used. Power can be gated using either header cells (which disconnect the Vdd) or footer cells (which disconnect the Ground).

State Retention
Capability to retain the critical state of sequential elements within a block when the block is powered down. State retention generally requires saving the registers and possibly memory contents of the block.

Unified Power Format (UPF) (IEEE-1801)
The IEEE-1801 (Unified Power Format) is an open industry standard for the specification of implementation-relevant power information early in the design process RTL (register transfer level) or earlier.

Voltage area
A physical representation of a power domain. Generally, it is recommended to have a one-to-one correspondence between power domains and voltage areas, although this is not a requirement.

Variable Threshold CMOS (VTCMOS)
Variation of the well voltage to adjust threshold voltage, which in turn increases speed (forward bias) or reduces leakage (backward bias). Also known as Variable Vth. (see well biasing).

Well Biasing
Separate voltage supplies can be used to connect to the NMOS and PMOS bulk regions in triple well CMOS technologies. Modification of these voltages with respect to the primary power and ground supplies is called well-biasing. These supplies can be modulated to provide a back-bias voltage which causes an increase in device Vth, reducing the sub-threshold leakage. These supplies can also be modulated in the reverse direction to provide a forward-bias voltage which causes a decrease in device Vth that increases the speed at which the transistors switch, at a cost of increased sub-threshold leakage. Thus, well-biasing can be used to directly adjust between high performance and low power consumption.