Power Reduction Techniques
Are they all the same for established planar, FD-SOI and finFET transistors?
Aug 07, 2014

Managing power intent, signal isolation and level shifting in a UPF-based multi-voltage IC design
Power intent, signal isolation and level shifting can all be controlled in a UPF-based multi-voltage IC design through careful coding.
Sep 17, 2013

Choosing a block representation in a UPF-based hierarchical multi-voltage IC design
This article looks at the way in which various representations of a block of a design have different implications in a UPF based power-aware hierarchical design flow.
Sep 03, 2013

Optimizing IP for Power
As the amount of commercial IP in an SoC increases, the entire bill of materials is coming under increasing scrutiny because of a new concern - power.
Apr 11, 2013

The Power Game
Semiconductor engineering are finding that maintaining the balance between higher performance and the same or lower power is increasingly onerous.
Apr 11, 2013

Version Control
There are so many different versions of specifications, formats and increasingly IP, some of which conflict directly with each other, that it may take months or even years before some customers adopt new products.
Mar 14, 2013

High Performance and Low Power Design: Tradeoff or Co-Existence?
The latest EDA innovations address the "Quadrangle of Constraints" design challenge.
Nov 19, 2012

Considerations for Writing UPF for a Hierarchical Flow
This article details the considerations that you need to take into account when writing UPF for a hierarchical design methodology.
Apr 06, 2012

Guest Editorial: Low Power is Everywhere
Apr 01, 2012

Insight Article Technology Update: Reducing Power with Advanced Synthesis
Dec 01, 2011

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