Articles 


A Silicon Interposer-based 2.5D-IC Design Flow, Going 3D by Evolution Rather than by Revolution
A Silicon Interposer-based 2.5D-IC Design Flow, Going 3D by Evolution Rather Than by Revolution Dr. Michael Jackson, VP of R&D and Physical Implementation at Synopsys ponders the 3D-IC technology trends, their timeline, and the impact on EDA, proposing that a silicon interposer-based 2.5D-IC design flow is well within our reach.
Mar 24, 2012

The Fast Track to 3D-IC Testing
Three-dimensional integrated circuit (3D-IC) systems offer the potential to deliver significant improvements in performance, power, functional density, and form factor over other packaging integration techniques. This article focuses on the test challenges and solutions, highlighting a design-for-3D-test architecture and implementation flow developed by researchers at Industrial Technology Research Institute (ITRI) based on the Synopsys test solution.
Jan 16, 2012

Synopsys Debuts DesignWare STAR ECC IP
Synopsys chose the International Test Conference to announce an expansion of its synthesis-based test technology and announced the availability of its DesignWare STAR ECC (self test and repair error-correcting codes) IP. The new STAR ECC IP is based on technology obtained through Synopsys's acquisition of Virage Logic.
Nov 06, 2010