All Synopsys News

Sep 08, 2013TSMC and Synopsys Extend Custom Design Collaboration into 16-nm
TSMC Certifies Laker Custom Design Solution for 16-nm FinFET and Provides iPDK

Oct 15, 2012Synopsys and TSMC Collaborate for 20nm Reference Flow
Design Tools in Synopsys® Galaxy™ Implementation Platform selected in 20nm Reference Flow for Physical Implementation, RC Extraction, Timing Analysis and Physical Verification

Jun 04, 2012Synopsys and Samsung Deliver a Complete Solution for 20-Nanometer Node
Solution Includes Place and Route, Physical Verification, and Signoff Design Tools

May 29, 2012TSMC Certifies Synopsys Design Implementation Tools For 20 Nanometers
Certified tools include IC Compiler, IC Validator, StarRC, PrimeTime and Custom Designer

Mar 28, 2012Synopsys' Collaboration with Industry Consortium Yields Double Patterning Technology Models for Parasitic Extraction
IMTAB Group in IEEE-ISTO Ratifies Interconnect Technology Format Extensions for 20nm

Dec 14, 2011Synopsys Enables Silicon Success for GLOBALFOUNDRIES First Complex 20nm Design
GLOBALFOUNDRIES Tapeout Reinforces Synopsys IC Compiler as the Leading Choice for 20 Nanometers

Jul 11, 2011Synopsys Leads the Way in Delivering Dual-Patterning-Compliant 20 nm IC Implementation Support
Builds on Award-Winning IC Compiler Zroute and IC Validator In-Design Physical Verification Technologies

Jul 11, 2011Synopsys Announces Milestone in 20-nm Collaboration with Samsung Electronics
Samsung successfully tapes out first 20-nm test chip using IC Compiler and In-Design Physical Verification with IC Validator

Jun 02, 2011Synopsys Collaborates with STMicroelectronics to Help Achieve Critical Milestone in 20-nm Design
ST Successfully Tapes Out First 20-nm Test Chip