Datasheets 

IC Validator
Signoff DRC/LVS tool architected and proven for in-design physical verification at leading-edge process nodes

IC Compiler Advanced Geometry
Comprehensive place and route system for 20nm and below designs

PrimeTime Static Timing Analysis
Golden timing signoff solution and environment

StarRC Parasitic Extraction
Industry leading parasitic extraction for digital and custom design

Galaxy Custom Designer
Modern-era choice for layout entry and editing, enabling users to meet the challenges of today's fast-moving nanometer designs