Exhibit Dates and Hours
Tuesday, March 17, 12:20 pm – 2:10 p.m. and 5:20 p.m. – 8:00 p.m.
Wednesday, March 18, 12:35 p.m. – 2:15 p.m.
Santa Clara Convention Center
Great America Ballrooms – J & K
Visit Synopsys at Booth #13
See a demo and fill out our survey to
enter a drawing to win a free HP Mini Mi Notebook PC!
Come visit Synopsys at Multicore Expo and learn more about system-level design.
Multicore Expo is a leading-edge technology conference and exhibition dedicated to delivering practical solutions for designs involving embedded multicore, multimedia, and graphics. The fourth annual Multicore Expo, being held March 16-19, 2009 at the Santa Clara Convention Center, will feature an exhibition, presentations, and panels addressing all the major issues in multicore processor design and implementation, including the effective use of multicore development and design tools. The conference will also cover practical details on implementing virtual machine technology, multicore operating systems, and the application of multicore technology to embedded graphics and multimedia. Further information is available at www.multicore-expo.com.
Synopsys' system-level solutions will show a versatile portfolio of system-level design tools, models and services to address pre-silicon software development, debug and verification of multicore designs using virtual platforms. Combined with solutions for algorithm design and analysis the Synopsys product portfolio accelerates product development for multicore designs, leading to significant time-to-market reduction.
- Drop by our booth (#13) at Multicore Expo to learn about the latest pre-silicon software development and verification, such as:
- Embedded software (hardware/software co-verification) technologies
- Using Virtual platforms for pre-silicon software development
- Multi-core debug on virtual platforms
Synopsys Activities at Multicore Expo
Tutorial: Power Management Communications in an Energy Conscious Era
Wednesday, March 18
3:45 p.m. – 4:15 p.m.
Electronic devices are some of the key components in both the load and generation side of the energy gap. Almost every nation in the world, developed or developing, is going through massive overhauls in its energy policies. These trends and regulations, such as the recent Energy Star guidelines, will fundamentally impact SoC designs for the next 5-10 years. ICs and SoCs will be at the center of implementing not only the new energy efficiency guidelines, but also play a vital role in monitoring, managing and monetizing energy.
This talk looks at emerging trends and practices in the dynamics of energy efficiency from the point of view of loads, sources and transmission networks. We will discuss trends such as local and alternate energy sources, direct DC transmission, smart grids and interactive loads/load groups. We will then discuss an integrated 'global-local' power management view, which will form the basis for a hardware/software platform to manage this infrastructure. We will then conclude with a example of a power management 'sideband' signaling scheme on SoCs and its software architecture. In particular, we will look at some of the impact on traditional heterogeneous multi-CPU SoCs and at emerging homogenous multi-core SoCs and processors.
Panel: Clock & Power Domain Control/Management Challenges in a Multicore World: The Interconnect Dilemma
Wednesday, March 18
4:20 p.m. to 5:25 p.m.
Srikanth Jadcherla, Synopsys
David Stratman, Silistix
Drew Wingard, Sonics, Inc.
Multicore SoC designs are experiencing rapid growth in both the number of discreet power and clock domains/islands, and the number of supported frequency and voltage combinations. As dynamic voltage and frequency scaling (DVFS) becomes the norm rather than the exception, how are these domains controlled and managed in a multicore system? How does the complex on-chip interconnect handle these dynamic changes while ensuring robust communication between critical system components? These topics and more will be discussed from the hardware and architectural perspective with a focus on power/clock control mechanisms and their impact on the chip interconnect. This panel brings together experts from the industry with detailed knowledge of interconnect IP, power control, and system management to discuss these challenges and trends facing the multicore community today.
Tutorial: Improving Multicore Software Development Productivity using Virtualization
Thursday, March 19
9:05 a.m. to 10:10 a.m.
Presenter: Frank Schirrmeister, Synopsys
With software development increasingly dominating the development effort, embedded software productivity and early start of software development have become crucial for product success. This trend is amplified by the rapid move to multi-core hardware platforms, which changes software development itself. Nominally multi-core hardware platforms increase the amount of processing performance but leave developers puzzled as to how to distribute software across multiple processors.
This presentation will illustrate how lack of control and visibility can limit embedded software development productivity in for multi-core designs. Specifically, hardware dependent multi-core debug challenges will be analyzed. The concept of virtual platforms for virtualization of embedded multi-core hardware will be introduced as a solution to improve productivity at the hardware/software interface. The presentation will illustrate how virtualization provides never before seen visibility into and control over the target hardware executing multi-core software, which is essential to optimize multi-core hardware development and embedded software debug.