|Optimizing DDR Memory Subsystem Efficiency - Part 1|
Part 1 – The Unpredictable Memory Bottleneck The memory subsystem sits at the core of a System-on-Chip (SoC) platform and can make all the difference between a well-designed system meeting its performance requirements and a system that delivers poor performance, or even fails to operate correctly. State-of-the-art DDR memory controllers use advanced arbitration and scheduling policies to optimize DDR memory efficiency. At the same time, they provide sophisticated Quality of Service (QoS) features to satisfy the specific bandwidth and latency requirements from individual SoC components. However, a large number of design parameters and configuration registers need to be tuned for the specific application to take advantage of these advanced capabilities.
Dr. Tim Kogel Solution Architect, Synopsys, Inc.
|Continuous Integration and Automation With Virtualizer Development Kits|
This whitepaper describes how simulation-based Virtualizer Development Kits are the perfect technology to remove the dependency with hardware and to enable the integration and testing of hardware dependent software (as well as full software stacks) in a continuous manner. A case study will illustrate the integration of VDKs with the most popular CI framework, Jenkins, and the most popular testing framework for Linux and ARM-based SoCs, LAVA, in the context of Linux kernel and device driver development.
Victor Reyes Technical Marketing Manager, Synopsys. Inc
|Optimizing DDR Memory Subsystem Efficiency - Part 2|
Part 2 – A Mobile Application Processor Case Study This whitepaper applies virtual prototyping tools and best practice techniques to optimize the DDR memory subsystem configuration for a specific SoC application. Starting from a hypothetical Mobile Application Processor design, we will illustrate step-by step how to optimize: Address mapping, Clock frequency, and Quality of Service (QoS).
Dr. Tim Kogel Solution Architect, Synopsys, Inc.
|Scaling Automated Software Testing With Virtualizer Development Kits|
In this whitepaper we will discuss how simulation-based Virtualizer Development Kits (VDKs) enable software to be tested in a system context much earlier, bridging the gap with unit and integration testing. Moreover, we will discuss how VDKs offer a more scalable solution as they consist of simulation models and hence alleviate the dependency on hardware labs.
Victor Reyes Technical Marketing Manager, Synopsys. Inc.
|Software Is Eating the World: End-to-End Prototyping to the Rescue|
The statement ‘software is eating the world’ was coined by internet pioneer Marc Andreessen in 2011. Over the last decade, the role of electronics in our daily life has changed dramatically.
Tom De Schutter, Senior Manager,Product Marketing,Virtual Prototyping, Synopsys, Inc.
|Is Your Automotive Software Robust Enough for Hardware Faults? Part 1: Fault Model and Effect Analysis Using Virtual Prototyping, Physical Modeling and Simulation|
In this whitepaper we describe how virtual prototyping is expanding its reach to improve development of safety critical systems and deal with the single most complex aspect of automotive systems: the embedded software.
Victor Reyes Technical Marketing Manager, Synopsys, Inc. and Kurt Mueller Manager, Corporate Application Engineer, Synopsys, Inc.
|Is Your Automotive Software Robust Enough for Hardware Faults? Part 2: Electrical Vehicle Powertrain Case Study for Virtual FMEA|
In this whitepaper, we will apply virtual Fault Mode and Effect Analysis (FMEA) concepts on a specific case study, an Electrical Vehicle Powertrain (EVP) system. We will show how this EVP system is refined from a Software-in-the Loop (SIL) level to a virtual Hardware-in-the-Loop level (vHIL), using a Virtualizer™ Development Kit (VDK). Hardware faults are applied to the resulting system and its response at both the hardware and software levels analyzed using our solution.
Victor Reyes Technical Marketing Manager, Synopsys, Inc. and Kurt Mueller Manager, Corporate Application Engineer, Synopsys, Inc
|Busting the 3 Big Common Myths About Physical Prototyping|
This white paper discusses several common misperceptions about physical prototyping with FPGAs and their inherit limitations have largely been eliminated by the capacity, automation, and infrastructure of modern commercial FPGA-based prototyping systems.
Troy Scott, Product Marketing Manager, Synopsys, Inc.
|Addressing IP Integration & Software Development Challenges to Accelerate SoC Time-to-Market|
This white paper will explore the issues facing SoC designers as they address SoC complexity and time-to-market challenges. It will discuss the use of third-party IP while noting that high-quality IP alone is not enough to accelerate time-to-market with today’s SoC complexity. The paper will also discuss issues around driver software development for the IP. Finally, it will review the five major development steps in any SoC design and how third-party IP providers should be expected to help accelerate each of these steps.
Dr. Johannes Stahl, Director of Prototyping Product Marketing, Synopsys, Inc.
|Using VDKs for Automotive Systems Development|
This white paper discusses the quantitative and qualitative analysis of the return on investment from VDKs. The software content of automotive systems found in powertrain, chassis, safety, body and advanced driver assistance systems (ADAS) application is increasing. At the same time, the pressure to accelerate development time lines, improve reliability and maintain/reduce costs is also increasing. Automotive OEM, Tier 1 and semiconductor companies involved in embedded software development, integration and test need to integrate new tools and methodologies in their development process to address these new challenges.
Marc Serughetti, Director of Business Development, Synopsys
|Advanced Power and Performance Optimization for Multicore SoCs|
The Multicore Optimization (MCO) technology in Synopsys Platform Architect provides an environment for early exploration and optimization of complex Multicore SoC (MP-SoC) platforms. It allows quantitative analysis of performance and power metrics to avoid SoC market failure due to underperforming or power hungry architectures.
Dr. Tim Kogel, Solution Architect, Synopsys, Inc.
|Using Virtual Prototypes to Address the Growing Software Complexity in Automotive|
This white paper explores how using virtual prototypes to model microcontrollers and electronic control units provide multiple benefits across the automotive supply chain. These include but are not limited to, the ability to develop software before hardware is available, the ability to integrate and test software stacks sooner and the ability to more thoroughly test functional safety aspects. Where time-to-market is the main driver for mobile applications, within the automotive industry the use of virtual prototypes aims mostly at improving quality and reducing safety risks, all while keeping the cost of software development and testing at bay.
Victor Reyes, Technical Marketing Manager, Synopsys Inc.
|Virtual Prototypes for Early Software Development: Requirements, Solutions and Use Cases|
"In previous white papers, we've looked at the demands of the rapidly changing market and how the use of virtual prototypes has evolved to help meet them. In this white paper, we look specifically at the challenges of developing some of the hardware-dependent software layers - namely boot ROM code, OS bring-up, driver development - used in fast-evolving mobile devices and how to use virtual prototypes to 1) Start developing software far in advance of hardware availability 2) Break the gating dependencies between layers in the software stack to enable parallelized development and 3) Develop the silicon validation suite before hardware is available."
Tom De Schutter, Product Marketing Manager, Synopsys, Inc. and Achim Nohl, Technical Marketing Manager, Synopsys, Inc.
|Virtual Hardware "In-the-Loop": Earlier Testing for Automotive Applications (Part 1)|
This whitepaper is the first one in a series of publications that will describe the concept of virtual hardware "in-the-loop" (vHIL). The goal of vHIL is to frontload the testing process by enabling software teams to create and run their software tests before the actual ECU hardware is available. Higher quality tests, higher quality software and a more streamlined "in-the-loop" flow is the intended outcome of this solution. Besides describing how vHIL fits in the general Model-In-the-Loop (MIL) - Software-In-the-Loop (SIL) - Hardware-In-the-Loop (HIL) process, this first whitepaper describes in more detail how a virtual prototype model created with Synopsys Virtualizer can be integrated with a MathWorks Simulink plant model. This integration is fundamental for enabling a vHIL solution.
ctor Reyes, Technical Marketing Manager, Synopsys Inc.
|Virtual Prototypes: When, Where And How To Use Them|
An innovation-hungry public and a highly competitive marketplace make for short product cycles, while the sophistication and performance expected of digital devices grows with every new product generation. Heterogeneous multiprocessing, where different cores do specialized work, has become the industry norm inside those devices, radically increasing the amount of software needed, the importance of software in managing system resources and the possibility for error among interconnected, interdependent subsystems. Traditional tools and methods for embedded software development are no longer up to the jobs software is being asked to perform within the schedules engineering teams are required to meet.
Tom De Schutter, Product Marketing Manager, Synopsys, Inc.
|Designing the Right Architecture|
In this white paper, we present a tool-assisted system-level performance analysis flow for interconnect and memory performance optimization using Synopsys Platform Architect. This environment allows the rapid creation of system-level performance models and the parallel simulation of many design configurations to investigate a wide range of architectural options. After a brief motivation and introduction of the flow we discuss the results of a design project, where Platform Architect has been used to optimize the performance of a multicore mobile platform SoC.
Tim Kogel, Solution Architect, Synopsys, Inc.
|The Power of Developing Hardware and Software in Parallel|
"Exploring trends in the highly competitive mobile device market and the highly regulated automotive industry, this paper will discuss the challenges device development teams face today and how virtual prototyping can help meet them."
Tom De Schutter, Product Marketing Manager, Synopsys, Inc.
|Virtual Prototyping for Energy Efficient Mobile Platform Design|
"This white paper introduces the complexity of power management at the software level for mobile devices by means of Linux and Android. The complexity of hardware power management is mirrored in software. A single defect in the power management scheme can have a catastrophic impact on the standby time of a mobile device. We outline how Synopsys Virtual Prototypes address major challenges in the bring-up and validation of power management software. Furthermore, we introduce how virtual prototypes can be used for software-centric power estimation and analysis. "
Achim Nohl, Technical Marketing Manager, Synopsys Inc. and Alan Gibbons, Principal Engineer, Synopsys Inc.
|Overcoming LTE PHY Design Challenges Using System-level Design Methodologies|
This white paper introduces some of the design challenges that may be encountered in designing the physical layer (PHY) for LTE and how Synopsys' DSP algorithm design tools create executable specs to overcome them.
Louie Valena, Corporate Applications Engineer, Nihon Synopsys G.K.
|Efficient Design and Verification of Digital Communication Systems|
LTE and WiMAX are key contenders for next generation mobile phone system. Both standards are excellent examples to highlight the huge complexity involved in modern communication algorithms. This increasing complexity is the trigger for new design methodologies and tools. This white paper provides a detailed analysis on the elements that determine algorithm design and verification efficiency for LTE and WiMAX communications systems. The concept of efficiency is discussed for modeling, simulation, reuse, and verification. Different methodologies and simulation solutions are then compared, providing the reader with specific algorithm design requirements.
Markus Willems, Ph.D., Product Marketing Manager, Synopsys and Holger Keding, Ph.D., Corporate Application Engineer, Synopsys
|C/C++ for Complex Hardware Design|
An increasing number of ASIC and FPGA designs are accelerating algorithms and applications directly in hardware (HW) circuits. These HW accelerator cores have become commonplace and are now a key part of product differentiation and the ability to meet market expectations in performance, cost and reliability. However, the implementation and verification of hardware acceleration cores is very difficult, especially due to the growing complexity of standards in video, imaging, wireless, and other multimedia and communications applications. RTL methodologies for IC design and verification are struggling to address this complexity in terms of productivity, available resources and time-to-market.
Chris Eddington Director of Marketing,High-Level Synthesis and System-Level Products,Synopsys, Inc.
|Debugging Embedded Software Using Virtual Prototypes |
Virtualization of Electronic Systems plays an increasingly important role for the design of today’s complex electronic systems. This article introduces the usage and benefits of Virtual Prototypes for debug and analysis during embedded software development.
Achim Nohl, Solution Architect, Synopsys, Inc.
|Debugging SuperSpeed USB Software Using Virtual Prototypes|
Software is a critical component for the development of USB-based designs. In efforts to start software development early and to make it as productive as possible, design teams are often utilizing virtual and FPGA prototypes for software development prior to silicon. While FPGA prototypes can still be made available prior to silicon, virtual prototypes can be utilized even before RTL is available. This white paper describes how virtual prototype use models for hardware/software verification and the integration of the LeCroy analyzer software into Synopsys' DesignWare SuperSpeed USB verification environments help solve SuperSpeed USB IP development challenges.
Frank Schirrmeister, Director, Product Marketing; Tri Nguyen, R&D Engineer
|Understanding the Real Cost of Prototyping Hardware|
This white paper provides an in depth look at significant factors to consider when choosing to develop or purchase prototyping hardware. Costs, development time, and effort are considered in detail as well as other factors such as bill-of-materials cost, manufacturing time, and test yield. The paper also provides information on how to request a “Cost Comparison Spreadsheet” which will allow you to explore the various options and make an informed decision for your particular situation.