HAPS®-70 Series   

Physical Prototypes with the Highest Performance and Scalable Capacity 

The HAPS-70 series is an easy-to-use and cost effective physical prototyping system. The HAPS-70 series enables early hardware/software integration and system-level validation at near-real-time run-rates, using at-speed, real-world interfaces.

HAPS-70 Product

For more information on the HAPS-70 series contact your local Synopsys sales office or send an email to physical-prototyping@synopsys.com.

HAPS-70 Features:
  • Modular system architecture, using Xilinx Virtex®-7 FPGAs, scales from 12 to 288 million ASIC gates to accommodate a range of design sizes, from individual IP blocks to processor sub-systems to complete SoCs. For system capacity ranging from 500k-4M ASIC gates, see the HAPS Developer eXpress (HAPS-DX) Series. For system capacity over 288 million ASIC gates, see the HAPS-80 Series.
  • Enhanced HapsTrak 3 I/O connector technology with high speed time-domain multiplexing delivers up to 3x performance improvement in data throughput over traditional pin multiplexing
  • System definition and bring-up utilities speed hardware assembly and ensure the prototype’s electro-mechanical integrity
  • Advanced power and cooling management
  • Design planning tools reduces time-to-prototype by 2-3 months streamlining the transition from block level IP validation to full system integration
  • High debug efficiency
  • Advanced use modes including hybrid prototyping
  • HAPS-70 systems are available in nine model variants, with capacities from 12 to 288 Million ASIC gates
  • Compatible with DesignWare IP Prototyping Kits
HAPS Accessories and Software

High Performance
Performance is what has made the HAPS family the industry leader for a range of validation scenarios from independent IP blocks to full systems that integrate CPU subsystems.

HAPS-70 Intro video

Scalable Capacity
A modular hardware architecture along with the latest high-capacity FPGA technology allows for HAPS-70 series systems to scale from 12-288M ASIC gates.

Deep Visibility
Seamless debug visibility across FPGAs and a spectrum of trace storage options allow you to deep access and control with minimal impact to prototyping resources.

HAPS Deep Trace Debug video

Easy Bring-Up
IP and ASIC RTL migration technology from the industry's leading EDA vendor reduces your effort to deliver high-performance prototypes.

Connectivity Options
The benefits of stand-alone physical prototypes are clear, but co-simulation and transaction-based validation connectivity for HAPS-70 eases migration from an RTL simulation environment and enable a hybrid system that integrates SystemC/TLM models for the fastest SoC prototype bring-up ever.

HAPS-Specific Design Planning Features
Regardless of the size of the prototyping project: an individual IP, subsystem, or a full system-on-chip, design planning tools for FPGA-based prototypes must be optimized for rapid bring-up. Design preparation and planning can be a time consuming task with schedule bottlenecks like:
  • Multiple iterations and long compile runtimes that delay the review of IP and HDL
  • Time consuming conversion of gated and generated clocks to fit FPGA clock architectures
  • Manual intervention to find a feasible partition across multiple FPGAs
  • Incremental project changes leading to time-consuming rebuilds
ProtoCompiler prototyping software for the HAPS-70 Series is designed to help minimize the time to first prototype with automation features that include:
  • HDL compiler modes to maximize HDL source code review efficiency
  • Clock conversion options for either very fast runtime or speed-optimized for best system performance
  • Parallel processing of FPGA partitioning and synthesis
  • Fast automated, constraint-driven partitioning and system-level routing
  • Virtually unlimited capacity
  • Database model allows for short iteration points
  • Efficient Tcl-based command interface
  • Automatic time-domain multiplexing of Xilinx Virtex-7 high-speed pin pairs

Learn more about the automation features provided by ProtoCompiler

Connectivity and Debug Features
ProtoCompiler RTL debugger and HAPS UMRBus (Universal Multi-Resource Bus) connects HAPS to a host workstation for system monitoring, RTL debug, and advanced verification. In addition to the features to ease RTL debugging of FPGAs, tight integration of HAPS systems allows Synopsys to offer unique solutions for high capacity debug and system connectivity:

  • Quickly assemble and confirm the integrity of multi-motherboard and daughter board systems with HAPS-Aware hardware query and checks for clock validity, HSTDM links, and UMRBus connections
  • Apply HAPS Deep Trace Debug (HAPS DTD) for up to 8 GBytes of sample storage
  • Improve prototype state visibility by data streaming between HAPS and a host workstation with HAPS UMRBus interface
  • Apply an external logic analyzer for sophisticated triggering and high-capacity sample storage. Use the HAPS Real Time Debug (RTD) option with a HAPS Probeless or Mictor-style daughter board to instrument RTL then easily program and connect Agilent or Tektronix Logic Analyzer to a HAPS system

Troubleshoot and Debug Made Easier
For additional information on HAPS Deep Trace Debug and other Synopsys tools that can help troubleshoot your physical prototype and quickly isolate RTL bugs.

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