Physical Prototyping 

Scalable Prototyping System Accelerates Hardware and Software Development 

Many design and validation teams are increasingly using physical prototyping to meet time-to-market windows. Synopsys' Physical Prototyping Solution improves time-to-market and helps avoid costly device re-spins by enabling early embedded software development and allowing hardware and software co-design well ahead of chip fabrication. Together, our suite of tightly integrated and easy-to-use HAPS hardware and HAPS ProtoCompiler tools dramatically accelerate software development, hardware/software integration and system validation from individual IP blocks to processor subsystems to complete SoCs.

HAPS systems are also supported by an ecosystem of third-party vendors from the Synopsys HAPS Connect Program that provide daughter boards, services and hardware for HAPS.


Uses Xilinx Virtex® UltraScale™ FPGAs for capacity over 1.6 billion ASIC gates

Uses Xilinx Virtex®-7 FPGAs for capacity up to 288 million ASIC gates

Uses Xilinx Virtex®-7 FPGAs for capacity up to 4 million ASIC gates

HAPS ProtoCompiler
Design Automation and Debug for the HAPS Series

Partition SoC design blocks between Virtualizer™ virtual prototyping and HAPS FPGA-based prototyping environments for best overall prototype performance and availability.

  • Certify
  • Multi-FPGA Partitioning Tool for 3rd Party HWmore

The Certify multi-FPGA implementation and partitioning tool combines RTL multi-chip partitioning with best-in-class FPGA synthesis.

Synplify Premier software enables easy conversion of ASIC-style designs and implementation into the HAPS prototyping system.

Synopsys Physical Prototyping Solution Brings It All Together
The Synopsys physical prototyping solution is a complete hardware-assisted system validation environment based on our HAPS® High-performance ASIC Prototyping System™ supported by a comprehensive design automation and debug environment called HAPS ProtoCompiler.

Benefits of the Synopsys physical prototyping solution include:
  • 3-6 months shorter design schedules by enabling earlier embedded software development
  • Eliminate redundant IP prototyping tasks by using pre-tested DesignWare IP components
  • Maximize ROI by applying the modular system across multiple projects
  • Lower risk with a proven solution with over 5000 units shipped across more than 400 customers
  • Improve product quality with a high-performance system that will support real-world interface testing
  • Portable and cost effective to deploy prototypes to software development teams
  • Freely combine RTL and other model formats like SystemC to create hybrid prototypes for even earlier availability
  • Immediate product availability using the latest generation of FPGA devices, bypassing bring-up effort and expense of custom-built systems
  • Reliable for maximum up-time with sophisticated PCB technology and advanced power and heat management
  • Easy deployment and sharing via a network connection and the HAPS UMRBus Interface Kit
Synopsys’ physical prototyping systems are used when synthesizable RTL models of the ASIC/system-on-chip design are available, allowing designers to develop software, verify SoC hardware and enable hardware/software integration before the silicon is taped-out. Hardware and software design teams can deploy HAPS® systems in a variety of roles in the SoC development cycle.

Speed-Up Design Under Test (DUT) Review:
The HAPS Series delivers multi-megahertz operation to help speed the review of RTL blocks that require high-volumes of test patterns to confirm operation. There are two popular use models, one with memory pre-load/readback of HapsTrak 3 memory daughter boards or direct streaming from the host workstation. The HAPS UMRBus supports both scenarios with a stable and high-performance physical link and APIs to ease integration between a host workstation and a HAPS system via a USB or PCIe connection. For DUT testing, preload and readback of on-board DDR3 SDRAM with test and result data is ideal for review of media codecs. The Synopsys SolvNet Catalog of HAPS Design Examples includes DUT test jigs that integrate DDR3 memory interface controller for the HapsTrak 3 8 GB memory module. The UMRBus API for Tcl/C/C++ makes adoption into your test environment easy and HAPS’ superior modularity and reusability allows you to focus on new design and verification tasks instead of developing custom test equipment.

Hardware/Software Co-Development:
By using a high-performance prototype, software development can begin much sooner in the design process. A HAPS Series system can achieve internal system frequencies in 100s of megahertz, making it feasible for SoC designs to execute the low-level firmware of the software stack, as well as the full operating system and even applications. When coupled with a Virtualizer™ virtual prototype, HAPS’ RTL subsystems run concurrently with SystemC/TLM-based processor models, creating a unique and powerful hybrid prototype that delivers the best of virtual and hardware prototyping methods.

End User Evaluation:
HAPS systems are light and portable. They can be powered with conventional power sources and quickly assembled in the field for customer demonstrations, industry conferences, “plug-fests”, and validation scenarios outside of the lab environment.

Prototyping Server Farms:
ASIC prototypes are now often integrated as a shared IT resource. In order to maximize the ROI and regression throughput the HAPS-80 Series incorporates sharing and management features to support both multi-design and remote shared usage scenarios. HAPS Multi-Design Management (MDM) features allow multiple independent designs to be programmed onto a multi-FPGA HAPS system. This helps HAPS users to avoid idle FPGAs and maximize utilization of multi-FPGA systems and a more parallel work flow. Integrated Ethernet interface and a runtime management server allow remote clients to attach to the system to assign and run designs to one or more FPGAs. This allows runtime scenarios for individual IP blocks, subsystems, or full SoC designs to be run concurrently.

Synopsys’ physical prototyping solutions enable pre-silicon embedded software development and hardware/software integration of complete systems and subsystems at near real-time operating speeds using real-world interfaces. The HAPS® High-performance ASIC Prototyping System™ is designed to support all of your ASIC prototyping needs, including hardware/software co-development, proof-of-concept studies, IP development and end-user evaluations. HAPS capabilities include:
  • Flexible, scalable and expandable system architecture – maximizes the reusability for multiple projects
  • Best-in-class quality and reliability – ensures the highest system performance and stability
  • Wide catalog of I/O interfaces including Gigabit PHYs – a deep catalog of HAPS Accessory daughter boards to interface to the physical world
  • HapsTrak standard – I/O connector standard that allows for backward and forward compatibility with previous and future generations of HAPS systems
  • High-speed Time-Domain-Multiplexing (TDM) – high-speed interconnect multiplexing increases bandwidth limiting effective capacity on FPGAs
  • Advanced verification functionality – includes co-simulation, transaction-based verification, and fast Universal Multi-Resource Bus (UMRBus) interface for high-speed design interaction and monitoring
  • Interoperable with DesignWare® IP Prototyping Kits – Synopsys offers support to merge multiple DesignWare IP’s into a subsystem with a HAPS-80 or HAPS-70 system as the integration point allowing teams to incorporate other major IP blocks with proprietary design elements

Visit the HAPS physical prototyping webpage for more information.

Synopsys’ physical prototyping software tools provide engineers with design planning, logic synthesis, and debug, tools to address the largest system-on-chip (SoC) designs. Synopsys physical prototyping software is applied by hundreds of design teams worldwide to maximize productivity when using HAPS systems.

Comprehensive Design Automation and Debug for the HAPS Series of Physical Prototypes
If you're involved with system validation or hardware/software integration tasks then you're painfully aware of the demanding prototype project schedule that drives engineers to deliver operational prototypes within weeks or even days following the RTL "drop" from the design and verification team. There is little time for delay and this focus on reducing the "time-to-first" prototype has influenced the design and usage model for the HAPS design environment, HAPS ProtoCompiler.

HAPS ProtoCompiler delivers key features and benefits to address both rapid prototype bring-up and fast system performance:

  • Parallel processing, runtime optimizations, and short design iteration loops allow designers to deliver an operational HAPS system within days of RTL/IP availability
  • Billion ASIC gate capacity to handle the highest-capacity HAPS Series systems ensures that you can support SoC/ASIC prototype projects today and in the future
  • Constraint-driven partitioning, high-speed time-domain multiplexing of FPGA I/Os, and system-level routing to maximize HAPS system clock performance
  • Flexible and high-capacity debug storage options for single or multi-FPGA debug maximizes visibility and sample rates available for HAPS systems
  • ARM AMBA compatible transactor-level interfaces ease implementation of hybrid prototypes

For more information on Synopsys physical prototyping software tools for custom-built ASIC prototypes, see Synplify Premier.

physical prototyping hardware/software flow
physical prototyping hardware/software flow

Synopsys' offers the industry’s broadest portfolio of silicon-proven IP solutions for SoC designs.

The interoperability of Synopsys HAPS extends to the DesignWare® IP Prototyping Kits available for a variety of popular interface IP including: USB, PCI Express, and DDR. DesignWare IP Prototyping Kits provide a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary SoC integration logic such as clock, reset, power management, and test logic for a specific IP protocol, implemented on a HAPS-DX Series system. All kits include reference drivers, SoC integration logic, and application examples.

Using DesignWare IP with HAPS eases common prototyping tasks, including:
  • Controller with PHY interoperability validation
  • System compliance tests
  • Subsystem integration
  • Firmware/software development

See live video demonstrations of DesignWare IP implemented on HAPS systems.

Get more detail about HAPS series daughter boards designed for interface and SoC validation

A unified design and prototyping flow for SoC designs that integrates Synopsys DesignWare® IP eases the migration from the RTL/IP design to either HAPS prototyping system or target ASIC silicon. The Synopsys coreConsultant tool guides the user from installation to a HAPS prototype using the HAPS ProtoCompiler software or an ASIC implementation using Synopsys Galaxy Implementation Platform.

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